S. Ecoffey

SETMOS: a novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs

We have proposed and validated a true hybrid SET/CMOS device, called SETMOS, that is able to extend the Coulomb blockade oscillations of a SET transistor into the /spl mu/A current range, corresponding to near sub-threshold operation region of a nanometer-scale MOSFET. New nano-scale analog applications, working at sub-ambient temperatures (-150/spl deg/C up to 100/spl deg/C), including a novel NDR circuit, amplifiers, and even NEMS-SETMOS circuit cells are uniquely supported by SETMOS.

Low-pressure chemical vapour deposition of nanograin polysilicon ultra-thin films

With this work we have assessed the minimum thickness and grain size realizable for a polysilicon (poly-Si) layer deposited with a low-pressure chemical vapour deposition technique. Three different approaches using pure silane in a standard horizontal reactor have been evaluated: (i) a direct poly-Si deposition, (ii) a hemispherical silicon grain deposition and (iii) an amorphous silicon (a-Si) deposition followed by crystallization thermal annealing. It has been demonstrated that the a-Si/crystallization process seems to be the best candidate for the deposition of ultra-thin poly-Si films. However, it involves process innovation in both the nucleation and annealing phases. With this method we have succeeded in the deposition of uniform 6 nm poly-Si layers with grain sizes around 10-20 nm.

A new logic family based on hybrid MOSFET-polysilicon nanowires

A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up to 400K and hybridized with conventional CMOS. Ultra low power dissipation in the order of hundreds of pWs has been observed, which is outperforming CMOS technology, in terms of power consumption, by orders of magnitude

Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits

N-doped polysilicon gated-nanowires (poly-SiNW) are reported. The V-shape and hysteresis of their I-V characteristics are used to build analog and memory circuit cells. Integration of the poly-SiNW in CMOS is demonstrated. A precise current-measurement application with 1pA resolution and negative differential resistor is reported. A nanoscale capacitor-less hysteresis memory cell using constant-current biased poly-SiNW is designed and experimentally validated.

LPCVD Deposition Techniques for Nanograin sub-10nm Polysilicon Ultra-thin Films

This paper investigates the limits of a low pressure chemical vapour deposition (LPCVD) technique for the deposition of a nanometre scale ultra-thin polysilicon (poly-Si) film with sub-10nm grain sizes. Three different processes using pure silane (SiH 4 ) in a standard horizontal hot-wall reactor are presented: (i) a direct poly-Si deposition, (ii) a Hemispherical Silicon Grain (HSG) deposition and (iii) an amorphous silicon (a-Si) deposition followed by a thermal crystallization anneal. The direct poly-Si deposition gives a minimum film thickness achievable around 20 nm with grain sizes ranging from 20 to 30 nm. The HSG deposition process leads to the formation of grains with diameters varying from 5 to 50 nm and heights ranging from 5 to 20 nm. The best results are obtained with the third process (a-Si / crystallization), which allows the formation of 6 nm poly-Si thick films with grain sizes ranging from 10 to 20 nm.

Emerging nanoelectronics: multi-functional nanowires

This talk aims to demonstrate that a silicon-on-insulator (SOI) nanowire technological platform could be a realistic approach to address the development of various types of multifunctional devices. Particularly, SOI nanowires could be a unique technological platform to co-fabricate: (i) nano-scaled solid-state MOS devices (such as the multi-gate MOSFETs); (ii) single-electron transistors and single electron memories; (iii) solid-state optoelectronic nano-scaled devices (modulators, optical switches, filters or even optical, interconnects for on-chip clock distribution...); and (iv) MEMS nano-resonators for full integrated RF IC functions. All these various categories of devices can take advantage of SOI intrinsic properties (technological toolset similar to silicon, natural lateral and vertical isolation, specific electrical, mechanical and optical properties) together with their aggressive scalability. Moreover, such, a technological platform could be hybridized with other nanotechnologies like molecular devices and carbon nanotubes. Some key examples, based on ongoing research projects at the Swiss Federal Institute of Technology Lausanne and world wide state-of-the-art was presented.

Electrical conduction in 10 nm-thin polysilicon wires from 4K to 400K and their operation for hybrid memory

This paper reports on the experimental investigation of conduction mechanisms in gated nanograins ultra-thin polysilicon nanowires (polySiNW) over a wide range of temperature: from 4K up to 400K. Some irregular Coulomb oscillations (CO) are observed at temperatures lower than 200K showing several period widths due to the random mixture in grain size (5-20nm). Remarkable results consist in more effective oscillations observed at higher drain voltages and, especially, at intermediate range of temperatures (between 50K and 150K). Finally, the V-shape (ambipolar) IDS-VGS characteristic and hysteresis of the polySiNW (maintained with high reproducibility) is exploited for building novel hybrid memory circuit cell.

Fabrication of polysilicon gated-nanowires and their application for pA precision current measurements

This paper reports on the fabrication and use of CMOS-compatible nanograin n-doped polysilicon gated-nanowires (polySiNW) for application in precise current measurements with less-than 1 pA resolution. A technological process is proposed to co-fabricate polySiNWs and n-channel MOSFETs. The investigation of the V-shape characteristic of I/sub D/-V/sub G/ extracted from fabricated polySiNWs is presented. A new bias scheme in order to use the nanowires as low current sensors is given. Finally, the effect of temperature on the conduction of polySiNWs is shown.

A study of fabrication techniques for sub-10nm thin undulated polysilicon films

For some single-electron memory architectures, room temperature operation requires a nano-grain ultra-thin (<10nm) and undulated polysilicon film as active region. This paper presents (i) several dry and wet etching techniques for fabricating ultra-thin polysilicon films with elevated contacts and (ii) two methods of undulating them, in order to obtain well-defined granular structures.