Pieter Harpe

13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS

This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP RF transceiver is one of the most critical components that enables these emerging applications, as it can consume up to 90% of total battery energy. Furthermore, a low-cost radio design with an area-efficient fully integrated RF SoC is an important catalyst for developing such applications. By employing a low-voltage digital-intensive architecture, the presented SoC is fully compliant with BLE and IEEE802.15.4 PHY/Data-link requirements and achieves state-of-the-art power consumption of 3.7mW for RX and 4.4mW for TX.

26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme

Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.

A 780–950 MHz, 64–146 µW Power-Scalable Synchronized-Switching OOK Receiver for Wireless Event-Driven Applications

An on/off keying receiver has been designed in 90 nm CMOS for low-power event-driven applications. Thanks to the synchronized-switching technique and power-efficient RF gain stages, this receiver achieves -86 dBm sensitivity (10 -3 bit error rate) at 10 kbps while consuming 123 μW from a 1 V supply. The receiver is highly scalable in data rates from 1 kbps at 64 μW to 100 kbps at 146 μW power consumption. The center frequency of the receiver can be also programmed from 780 to 950 MHz, covering different sub-GHz bands worldwide. The receiver is fully integrated, although an external SAW filter can be added for better selectivity.

21.2 A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC

Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.

9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications

The introduction of the IEEE802.15.6 standard (15.6) for wireless-body-area networks signals the advent of new medical applications, where various wireless nodes in, on or around a human body monitor vital signs. Radio communication often dominates the power consumption in the nodes, thus low-power transceivers are desired. Most state-of-the-art low-power transceivers support only proprietary modes with OOK or FSK modulations, and have poor sensitivity or low data rate [1,2]. In this work, a 15.6-compliant transceiver with enhanced performance is proposed. First, the data-rate is extended to 4.5Mb/s to cover multi-channel EEG applications. Second, while a best-in-class energy efficiency of 0.33nJ/b is achieved in the high-speed mode, a dedicated low-power mode reduces the RX power further in low-data-rate operation. Third, a sensitivity 5 to 10dB better than the 15.6 specification is targeted to accommodate extra path loss due to shadowing effects from human bodies.

24.4 A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1μW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.

A 680 nA ECG Acquisition IC for Leadless Pacemaker Applications

A sub- μW ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA and achieves CMRR >90 dB, PSRR >80 dB, an input-referred noise of 4.9 μVrms in a 130 Hz bandwidth, and has rail-to-rail DC offset rejection. Low-power heartbeat detections are evaluated with the help of the ASIC acquiring nearly 20,000 beats across 10 different records from the MIT-BIH arrhythmia database. In the presence of muscle noise, both the average Sensitivity (Se) and Positive Predictivity (PP) show more than 90% when the input SNR >6 dB.

A 71GHz RF energy harvesting tag with 8% efficiency for wireless temperature sensors in 65nm CMOS

This paper presents the first monolithically integrated RF-power harvesting 71 GHz wireless temperature sensor node in 65nm CMOS technology, containing a monopole antenna, a 71 GHz RF power harvesting unit with storage capacitor array, an End-of-Burst monitor, a temperature sensor and an ultra-low-power transmitter at 79 GHz. At 71 GHz, the RF to DC converter achieves a power conversion efficiency of 8% for 5 dBm input power.

15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation

Autonomous wireless sensor nodes need low-power low-speed ADCs to digitize the sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<;10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensitivity and a stable supply-independent full-scale range. However, solutions for efficient reference voltage generators (RVGs) are typically ignored in low-power ADC publications. In reality, due to the low power supply (usually sub-1 V) and limited available power (nW-range), the RVG is a challenge within the sensor system. In this work, a 2.4fJ/conversion-step SAR ADC with integrated reference is implemented. The 0.62V CMOS RVG consumes 25nW. To further reduce RVG power, it can be duty-cycled down to 10% with no loss in ADC performance. Additionally, the ADC uses a bidirectional dynamic comparator to improve the power efficiency even more.

A 430nW 64nV/vHz current-reuse telescopic amplifier for neural recording applications

This paper presents a low-power low-noise amplifier for neural recording applications. A single-stage current-reuse telescopic topology is proposed to achieve high DC gain and improve the noise efficiency factor (NEF) while allowing the amplifier to be scaled for high bandwidth sensing applications and/or to achieve lower thermal noise floor. The design is fabricated in a standard 0.18μm CMOS process and occupies an active area of 0.16mm2. Experimental measurements show a 430nW power consumption from a 1.2V supply, a thermal noise floor of 63.8nV/√Hz and a corresponding NEF of 1.5.