Po-Cheng Wu

An efficient architecture for two-dimensional inverse discrete wavelet transform

This paper proposes an efficient architecture for the two-dimensional inverse discrete wavelet transform (2D IDWT). The proposed architecture includes an inverse transform module, a RAM module, and a multiplexer. In the inverse transform module, we employ the coefficient folding technique and the polyphase decomposition technique to the interpolation filters of stages 1 and 2, respectively. The RAM size is N/2/spl times/N/2. The advantages of the proposed architecture are the 100% hardware utilization, fast computing time, regular data flow, and low control complexity, making this architecture suitable for next generation image coding/decoding systems.

A Novel MPEG-2 Audio Decoder With Efficient Data Arrangement And Memory Configuration

The paper describes a novel MPEG-2 audio decoder with a new modified scheme. In the techniques of intelligent data arrangement, the complexity of the multichannel decoding can be largely reduced. In the modified decoding scheme, the bottleneck computation module can be reduced to a quarter of the size of the original. Also, the major memory storage only requires half the size of the standard synthesis subband filterbank.

A multimedia video conference system: using region base hybrid coding

In this paper, a video coding algorithm suitable for video conference application, and an investigation of a video conference system over a LAN are presented. The proposed video coding algorithm is called the region base hybrid coding algorithm. This method can perform foreground and background segmentation. This is based on the characteristic of an unchanged background on most of the video conference applications. This property can reduce both data rate and computation load. The proposed algorithm is verified on a video conference system over a LAN, and it can work successfully.

Vlsi Implementation Of The Motion Estimator With Two-dimensional Data-reuse

This paper describes the VLSI implementation with a two-dimensional (2-D) data-reuse architecture for a full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

A novel scalable architecture with memory interleaving organization for full search block-matching algorithm

This paper describes a high-throughput scalable architecture for full-search block-matching algorithm (FSBMA). The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. By use of the efficient PE-rings and the intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Techniques for reducing interconnections and external memory accesses are also presented. Our results demonstrate that the scalable PE-ringed architecture is a flexible and high-performance solution for FSBMA.

A novel video signal processor with programmable data arrangement and efficient memory configuration

This paper describes a novel video signal processor (VSP) with a fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of a programmable data arrangement and an intelligent memory configuration. Techniques for reducing the interconnections and external memory accesses are also presented. A configuration of random-access on-chip memory modules solves the problems of chip I/O and memory bandwidth requirement. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.

A flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

An efficient architecture for two-dimensional discrete wavelet transform

This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform-module, we employ the polyphase decomposition technique to the decimation filters of stage 1, and the coefficient folding technique to the decimation filters of stage 2. The RAM size is N/2/spl times/N/2. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are the near 100% hardware utilization, fast computation time, regular data flow, and low complexity control circuit, making this architecture suitable for next generation image compression systems.

Vlsi Implementation Of Visual Block Pattern Truncation Coding

The paper proposes a pipelined architecture of a visual block pattern truncation coding algorithm to minimize the mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for moving pictures.

Hardware efficient design of filter banks for video coding

Since three-dimensional (3-D) subband coding has been introduced, most researches on 3-D subband coding perform temporal filtering first. In this paper, we investigate the best permutation strategy for temporal, vertical, and horizontal filtering to minimize the requirement of delay elements and find that the results are opposite to our expectation.