Po Chin Huang

Comparison of the trap behavior between ZrO 2 and HfO 2 gate stack nMOSFETs by 1/f noise and random telegraph noise

Low-frequency (1/<i>f</i>) noise characteristics of 28-nm nMOSFETs with ZrO₂/SiO₂ and HfO₂/SiO₂ dielectric gate stacks have been investigated. The observed lower 1/<i>f</i> noise level in ZrO₂ devices, as compared with that in HfO₂ devices, is attributed to the reduction in tunneling attenuation length and in trap density simultaneously. Experimental results showed that the trap behavior of ZrO₂/SiO₂ dielectric gate stack changes not only the trap location from a high-<i>k</i> layer to a SiO₂ interfacial layer but also the noise-dominated mechanism from carrier number fluctuation to the unified fluctuation model, which includes number fluctuation and correlated mobility fluctuation.

Investigation of Low-Frequency Noise Characterization of 28-nm High-k pMOSFET with Embedded SiGe Source/Drain

We have studied the low-frequency noise characterizations in 28-nm high-k (HK) pMOSFET with embedded SiGe source/drain (S/D) through noise and random telegraph noise measurements simultaneously. It is found that uniaxial compressive strain really existed in HK pMOSFET with embedded SiGe S/D. The compressive strain induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth from Si/SiO2 interface to the HK layer, so that the oxide traps at a distance from insulator/semiconductor interface cannot capture carrier in the channel. Consequently, lower noise level in HK pMOSFET with embedded SiGe S/D is observed, thanks to the less carrier fluctuations from trapping/detrapping behaviors. This result represents an intrinsic benefit of HK pMOSFET using embedded SiGe S/D in low-frequency noise characteristics.

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In this paper, for the hybrid orientation technology (HOT), we propose a modified amorphization/templated recrystallization (ATR) process to improve the material quality. The characterization of Si/SiO2 interface properties for complementary metal-oxide-semiconductor (CMOS) devices fabricated on HOT wafers is demonstrated through charge pumping (CP) and low-frequency (1/f) noise measurements simultaneously. For n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs), devices with the increased defect-removal annealing time bring out a significant decrease in the CP current and the 1/f noise. The results indicate that ATR-induced defects are further repaired and consequently achieve a well Si/SiO2 interface. In addition, the driving current improvement is observed in devices with a small dimension utilizing the modified ATR process. For p-type MOSFETs (pMOSFETs), the direct-current characteristic, CP, and 1/f noise results are comparable between both HOT wafers. It means that the modified process would not affect bonded (110) regions and degrade the device performance. Hence, this modified process could be adopted to improve the fabrication of the CMOS on the HOT wafer using the ATR method. Moreover, the physical origins of the 1/f noise is attributed to a fluctuation in the mobility of free carriers for pMOSFETs and a unified model, incorporating both the carrier- number and correlated mobility fluctuations, for nMOSFETs.

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In this letter, the effect of adding ZrO2 to different positions in an HfO2-based high-k (HK) gate-stack is investigated by a low-frequency (1/ f ) noise measurement. The tested nMOSFETs are fabricated using 28-nm gate-last HK/metal-gate technology with a ~ 1-nm SiO2 interfacial layer. The 1/f noise mechanism of these devices is described by the carrier number fluctuation, and the extracted trap densities (Nt)are 8.9 × 1018-5.1 × 1019 eV-1 cm-3. However, reference devices with a pure ZrO2 gate dielectric exhibit 1/f noise characteristics that are consistent with the unified model, which incorporates both the carrier number and the correlated mobility fluctuations. The reference devices are with lower Nt values in the range of 5.8 × 1017-2.4 × 1018 eV-1 cm-3. In addition, there is an increase in Nt as the initial HfO2 layer becomes thicker.These results show that the trapping behavior is mainly dominated by the HfO2 film and is dependent on the thickness of the initial HfO2 layer in the ZrO2/HfO2/SiO2gate-stack.

Interface Properties for CMOS Fabricated on Hybrid Orientation Substrate Using Amorphization/Templated Recrystallization (ATR) Method

In this study, the trap properties of composite Hf0.83Zr0.17O2 high-k gate stack p-type MOSFETs (pMOSFETs) were investigated by simultaneous low-frequency (1/f) noise and random telegraph noise measurements. Compared with pure ZrO2 pMOSFETs, the interface property and drive current of Hf0.83Zr0.17O2 pMOSFETs were both improved, and the depth of the effective centroid of the fixed charges was close to the insulator/semiconductor interface. This result indicated that the trapping behavior of hole capture from a ZrO2 film can be suppressed by mixing the film with a HfO2 film. Consequently, comparable oxide trap densities and trapping depths between Hf0.83Zr0.17O2 and HfO2 pMOSFETs can be seen. In addition, it was found that the unified model can appropriately interpret the 1/f noise mechanism in Hf0.83Zr0.17O2 pMOSFETs.

Low-frequency noise characteristics for various ZrO2-added HfO2-based 28-nm High-k/metal-gate nMOSFETs

The temperature dependence of the electrical characteristics of strained nMOSFETs combining stress memorization technique (SMT) process and contact etch-stop layer has been investigated. The observed higher mobility and lower gate tunneling current of SMT devices indicate higher tensile stress in the channel and prove the true transmission of SMT-process-induced stress from the deposited SiN layer. Moreover, as temperature is increased, SMT devices show less deteriorated mobility and increased gate tunneling current, which are due to decreased phonon scattering and increased tunneling barrier height, respectively.

Investigation of trap properties of Hf0.83Zr0.17O2 high-k gate stack p-type MOSFETs by low-frequency (1/f) noise and random telegraph noise analyses

The impact of aluminum ion implantation (Al I/I) on the 1/f noise and random telegraph noise (RTN) characteristics of high-k/metal gate (HK/MG) pMOSFETs is investigated. The Al I/I technology was implemented to tune the effective work function (EWF) of pMOSFETs without increasing the equivalent oxide thickness and complicating the process. The RTN and 1/f noise results showed that irrespective of the implanted dose, the HK/MG devices with Al I/I still exhibit lower slow oxide trap densities for the control device, because the Al filled the defect and formed a thin Al2O3 layer. In addition, for the HK/MG devices with different implanted doses, no significant differences in the trap properties are noted. However, the modulated EWF can be attributed to the Al I/I-induced dipoles at the HfO2/SiO2 interface.

Temperature Dependence of Electrical Characteristics of Strained nMOSFETs Using Stress Memorization Technique

In this research, trap properties in n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with different annealing sequences have been studied on the basis of low-frequency (1/f) noise and random telegraph noise (RTN) analyses. The 1/f noise results indicate that the source of the drain current fluctuation is electron trapping. The higher trap density in the devices annealed before the TaN layer causes serious noise and lower trap energy in RTN results. The substitution mechanism explains that the increment of defects is due to the additional nitrogen atoms in HfO2. On the contrary, fewer defects in the devices annealed after the TaN layer are due to the effect of passivation in the TiN layer. The defect in HfO2 is the source of trapping/detrapping; thus, fewer defects cause the decrement of the fluctuation and the increment of the drain current. We believe that this process has a potential to remove defects in advanced MOSFETs.

Impact of Aluminum Ion Implantation on the Low Frequency Noise Characteristics of Hf-Based High- \(k\) /Metal Gate pMOSFETs

In this letter, the effect of adding ZrO2 to different positions in an HfO2-based high-k (HK) gate-stack is investigated by a low-frequency (1/ f ) noise measurement. The tested nMOSFETs are fabricated using 28-nm gate-last HK/metal-gate technology with a ~ 1-nm SiO2 interfacial layer. The 1/f noise mechanism of these devices is described by the carrier number fluctuation, and the extracted trap densities (Nt)are 8.9 × 1018-5.1 × 1019 eV-1 cm-3. However, reference devices with a pure ZrO2 gate dielectric exhibit 1/f noise characteristics that are consistent with the unified model, which incorporates both the carrier number and the correlated mobility fluctuations. The reference devices are with lower Nt values in the range of 5.8 × 1017-2.4 × 1018 eV-1 cm-3. In addition, there is an increase in Nt as the initial HfO2 layer becomes thicker.These results show that the trapping behavior is mainly dominated by the HfO2 film and is dependent on the thickness of the initial HfO2 layer in the ZrO2/HfO2/SiO2gate-stack.

Effect of Annealing Process on Trap Properties in High-k/Metal Gate n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors through Low-Frequency Noise and Random Telegraph Noise Characterization

In this paper, we report on the low-frequency (1/f) noise characteristics of uniaxial tensile-strained nMOSFETs operated at high temperatures. We observed a small temperature sensitivity of 1/f noise in strained nMOSFETs. This can be attributed to the reduced tunneling attenuation length, suppressed phonon scattering, and increased mobility, which result from the strain-increased band splitting between the low-energy Δ2 valleys and high-energy Δ4 valleys. In addition, regardless of temperature, we found that the dominant mechanism of 1/f noise can be appropriately interpreted using the unified model, which incorporates both the carrier fluctuation and the correlated mobility fluctuation.