Praveen Kumar Venkatachala

A 0.6mW 31MHz 4 th -order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS

A highly compact low-pass filter (LPF) using self-coupled source follower based biquads is presented. The biquad cell synthesizes a 2nd-order low-pass transfer function in a single branch, using only two capacitors and a source follower with embedded local feedback for excellent linearity. A 4th-order Chebyshev LPF prototype is designed with a cascade of two biquads in 0.18μm CMOS, and occupies an active area of 0.1mm2. A cut-off frequency of 31MHz is measured with a stop-band rejection of 76dB. The prototype filter draws only 0.46mA current from a 1.35V supply, and achieves an in-band IIP3 of +29dBm. The averaged in-band input-referred noise is 22.8nV/√Hz, resulting in a dynamic range of 71dB.

A multi-path ring amplifier with dynamic biasing

This paper presents a new method for ring amplifier biasing to improve their stability while maintaining high slew rate. A multi-path ring amplifier is proposed for switched capacitor applications that allows accurate charge transfer at high speeds. Dynamic biasing improves large signal slewing without affecting residue amplifier settling performance. Stable operation is possible because the auxiliary path turns off dynamically, allowing the main path to be optimized for accuracy. The proposed multi-path amplifier was used in the first stage of a pipelined ADC in 180nm CMOS. Measurements show SNDR, SNR, and SFDR of 73.6 dB, 74.6 dB and 85.5 dB respectively, sampled at 10 MS/s, and consumes 7.68 mW.

Voltage domain correction technique for timing skew errors in time interleaved ADCs

A voltage domain correction technique is proposed to mitigate the timing skew errors in time interleaved (TI) analog to digital converters (ADCs). The proposed technique exploits the fact that any timing skew in the sampling edge of a clock results in a corresponding error in sampled voltage that propagates through the ADC. The technique intends to cancel this voltage error by applying a correction voltage at the input sampling network in a TI-ADC. The effectiveness of the technique is demonstrated by using behavioral models of a 14-bit 500MS/s 2 channel TI-pipelined-ADC.

A highly compact wideband continuous-time transimpedance low-pass filter

A highly compact continuous-time transimpedance low-pass filter (TILPF) topology is proposed that achieves a low input impedance and a 2nd-order transfer function in a single stage. This is suitable to perform current-to-voltage conversion with a built-in filtering characteristic in a passive mixer based wireless receiver. A 4th-order Butterworth prototype is designed with a cascade of the proposed TILPF and a self-coupled source follower based biquad in a 65nm CMOS. Operating with a 1.3V supply, the filter achieves 30MHz bandwidth while consuming 0.5mA total current. The simulated in-band IIP3 is +17.1dBm, and the average output noise is 14.2nV/√Hz.

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier

Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved inverters in the intermediate stage. This structure allows for the implementation of a dynamic deadzone that allows a single amplifier to perform both coarse estimation and fine settling. A pipelined ADC with a sampling speed of 20 MSPS is implemented in 0.18um CMOS. The ADC consumes 2.74 mW and achieves a peak SNDR of 74.33 dB which provides a FoM of 32.2 fJ/c-step with no calibration required.

A 7.5mW 35–70MHz 4th-order semi-passive charge-sharing band-pass filter with programmable bandwidth and 72dB stop-band rejection in 65nm CMOS

This paper proposes a highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that uses a semi-passive charge-sharing technique. It uses only switches, capacitors, digital circuitry for 3-phase non-overlapping clock generation and linearity-enhanced gm-stages. A 4th-order BPF prototype operating at 1.2GS/s sampling rate is implemented using a cascade of two independent biquads in a 65nm LPE CMOS. A tunable center frequency of 35-70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The in-band 1-dB compression point is -2.4dBm, and the in-band IIP3 is +9dBm. The filter prototype consumes 7.5mW from a 1.2V supply, and occupies an active area of 0.17mm2.