Jason Muhlestein

Analysis of metastability errors in asynchronous SAR ADCs

Previous work has provided detailed analysis of metastability errors and SMR for synchronous SAR ADC. This work extends the analysis to the Asynchronous SAR (ASAR), for which metastability errors are more difficult to understand and quantify. Since the relationship between SMR and conversion time cannot be reduced to a closed-form solution, a framework is instead provided for using numerical simulation results to determine the necessary conversion time such that metastability errors will not limit resolution. Two main contributions are made using this framework: first, the designer may determine the maximum effective sample rate for the ADC (and therefore the speed benefit over the synchronous SAR); second, it is shown that proximity detectors are not effective solutions to improving metastability performance.

Stochastic approximation register ADC

In this paper a stochastic approximation register ADC is proposed. The ADC is capable of achieving an ENOB of up to 10 bits. The ADC is composed of a variable noise engine, a bank of comparators with Gaussian offset noise, and a DAC. The ADC is simulated to achieve over 10 ENOB across various non-idealities using a comparator bank containing 1200 digital-cell based comparators with an input referred offset standard deviation of 12 mV.

Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs

A practical model for characterizing comparator metastability errors in SAR ADCs is presented, and is used to analyze not only the conventional SAR but also LSB-first and asynchronous versions. This work makes three main contributions: first, it is shown that for characterizing metastability it is more reasonable to use input signals with normal or Laplace distributions. Previous work used uniformly-distributed signals in the interest of making derivations easier, but this simplifying assumption overestimated SMR by as much as 18 dB compared to the more reasonable analysis presented here. Second, this work shows that LSB-first SAR ADCs achieve SMR performance equal to or better than conventional SARs with the same metastability window, depending on bandwidth. Finally, the analysis is used to develop a framework for calculating the maximum effective sample rate for asynchronous SAR ADCs, and in doing so demonstrates that proximity detectors are not effective solutions to improving metastability performance.

A VCO-based spatial averaging stochastic ADC

This paper proposes a spatial averaging stochastic oversampling ADC. By implementing VCO-based quantizers in parallel, the stochastic spatial averaging is inherently obtained along with 1st-order noise shaping. In an open-loop oversampling configuration which eliminates power- and speed-constrained active components, the proposed ADC only requires digital components which are easily synthesizable. Both uncorrelation conditions and spatial averaging characteristics are verified in a behavioral model. Some critical design insights are examined using design parameters from a 65nm technology.

A multi-path ring amplifier with dynamic biasing

This paper presents a new method for ring amplifier biasing to improve their stability while maintaining high slew rate. A multi-path ring amplifier is proposed for switched capacitor applications that allows accurate charge transfer at high speeds. Dynamic biasing improves large signal slewing without affecting residue amplifier settling performance. Stable operation is possible because the auxiliary path turns off dynamically, allowing the main path to be optimized for accuracy. The proposed multi-path amplifier was used in the first stage of a pipelined ADC in 180nm CMOS. Measurements show SNDR, SNR, and SFDR of 73.6 dB, 74.6 dB and 85.5 dB respectively, sampled at 10 MS/s, and consumes 7.68 mW.

A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization

This work describes a Nyquist rate ADC based on a two-step voltage and time quantization technique which can reduce power consumption and improve scaling immunity for high resolution applications. The hybrid two-step approach uses a successive approximation register (SAR) ADC for coarse quantization in the voltage domain, and a time-to-digital converter (TDC) for fine quantization in the time domain. The residue amplifier is suited for deep submicron CMOS due to its low gain and small output swing requirements, allowing the use of a single stage architecture. A 20MS/s prototype was designed and implemented in 180nm CMOS. Measurement results demonstrate an SNDR of 73dB. Operating with a reference voltage of 1.6V and a TDC supply of 1.0V, the total power is 1.28mW. This results in a Walden figure-of-merit (FOMw) of 17.4 fJ/conversion-step.

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier

Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved inverters in the intermediate stage. This structure allows for the implementation of a dynamic deadzone that allows a single amplifier to perform both coarse estimation and fine settling. A pipelined ADC with a sampling speed of 20 MSPS is implemented in 0.18um CMOS. The ADC consumes 2.74 mW and achieves a peak SNDR of 74.33 dB which provides a FoM of 32.2 fJ/c-step with no calibration required.

A 0.65mW 20MHz 5 th -order low-pass filter with +28.8dBm IIP3 using source follower coupling

A highly linear continuous-time low-pass filter (LPF) topology using source follower coupling is presented with excellent power efficiency. It synthesizes a 3rd-order low-pass transfer function in a single stage using coupled source followers and three capacitors, and can be configured to 2nd-order by disconnecting a capacitor. A 5th-order Butterworth prototype is designed with a cascade of two stages in 0.18μm CMOS, and occupies a core area of 0.12mm2. Operating with a 1.3V supply, the filter consumes 0.5mA current, and achieves a bandwidth of 20MHz with 82dB stop-band rejection. The measured in-band nP3 is +28.8dBm. The dynamic range is 74dB, with 15.3nV/VHz averaged in-band input-referred noise.

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers

A reference-free stochastic ADC is proposed by utilizing both spatial averaging and oversampling noise-shaping schemes. By implementing multiple VCO-based quantizers in parallel, stochastic spatial averaging for quantization errors is inherently obtained. In addition, 1st-order noise shaping of a VCO-based quantizer is achieved in an open-loop oversampling configuration. By resolving a faster conversion rate, this open-loop structure eliminates biasing, loop filter, sample-and-hold, and external reference, and it consists of only delay cells and digital logic. The proof-of-concept prototype which includes eight VCO-based quantizers and spatial averaging estimator is implemented in a 0.18 μm CMOS process, demonstrating 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, with 116 mW power consumption. Measurement results reveal that the eight channel stochastic ADC provides an average 9 dB SQNR improvement due to the spatial averaging.

Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters

This paper analyzes the effect of bit error rate on ADC performance and presents triple modular redundancy method for data converters. A comparison among different analog to digital converters (including successive approximation register, algorithmic/cyclic, and pipeline ADC architectures) are discussed. It is shown that a multi-path architecture provides the ability to measure and correct bit errors, squaring the bit error performance without additional analog area or power. We provide a comparative study of bit error rate among the different architectures and an error power calculation method that may be applied to further variations on these architectures, without time-consuming transient simulations.