Spencer Leuenberger

A 0.6mW 31MHz 4 th -order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS

A highly compact low-pass filter (LPF) using self-coupled source follower based biquads is presented. The biquad cell synthesizes a 2nd-order low-pass transfer function in a single branch, using only two capacitors and a source follower with embedded local feedback for excellent linearity. A 4th-order Chebyshev LPF prototype is designed with a cascade of two biquads in 0.18μm CMOS, and occupies an active area of 0.1mm2. A cut-off frequency of 31MHz is measured with a stop-band rejection of 76dB. The prototype filter draws only 0.46mA current from a 1.35V supply, and achieves an in-band IIP3 of +29dBm. The averaged in-band input-referred noise is 22.8nV/√Hz, resulting in a dynamic range of 71dB.

Analysis and performance trade-offs of linearity calibration for stochastic ADCs

Stochastic flash analog-to-digital converters (ADCs) have been proposed as a solution to the scalability problems encountered by a standard flash ADC. Instead of generating comparator references with a well-matched resistor ladder, it generates randomly distributed thresholds using either the comparator offsets or a separate noise-generating circuit. This allows all devices to be minimum size without matching problems; consequently the stochastic ADC becomes an attractive solution for a synthesizable ADC design. This work achieves two goals: first, it derives the relationship between the number of comparator decisions and effective resolution of a stochastic ADC with an arbitrary probability distribution function (PDF) of comparator thresholds. Second, this work identifies the conditions under which linearity calibration will improve performance. Monte-Carlo simulations demonstrate that for high signal amplitude or numbers of comparisons, calibration significantly improves resolution. For low amplitudes or numbers of comparisons, the ADC performs better without linearity calibration.

Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers

This paper proposes a new continuous-time (CT) MASH delta sigma (ΔΣ) modulator topology in which dual VCO-based quantizers are incorporated. The nonlinearity of both voltage-controlled oscillators (VCOs) caused by their nonlinear voltage-to-frequency (V-to-F) transfer curve are systematically suppressed without any calibration schemes. After the input voltage is directly digitized by a VCO-based quantizer (VCOQ), the residue error, obtained through passive subtraction with a current digital-to-analog converter (DAC), contains its noise-shaped quantization noise as well as the harmonics. This residue error is subsequently processed for fine digitization via a 2nd-order CT ΔΣ modulator where a second VCOQ is incorporated. The harmonics in the first VCOQs output are fully cancelled at the final digital output, which is collected by summing together the digital bits of the two VCOQs. Behavioral-model simulations demonstrate a 49dB SNDR improvement from the first VCOQ of only 39.3dB SNDR.

A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization

This work describes a Nyquist rate ADC based on a two-step voltage and time quantization technique which can reduce power consumption and improve scaling immunity for high resolution applications. The hybrid two-step approach uses a successive approximation register (SAR) ADC for coarse quantization in the voltage domain, and a time-to-digital converter (TDC) for fine quantization in the time domain. The residue amplifier is suited for deep submicron CMOS due to its low gain and small output swing requirements, allowing the use of a single stage architecture. A 20MS/s prototype was designed and implemented in 180nm CMOS. Measurement results demonstrate an SNDR of 73dB. Operating with a reference voltage of 1.6V and a TDC supply of 1.0V, the total power is 1.28mW. This results in a Walden figure-of-merit (FOMw) of 17.4 fJ/conversion-step.

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier

Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved inverters in the intermediate stage. This structure allows for the implementation of a dynamic deadzone that allows a single amplifier to perform both coarse estimation and fine settling. A pipelined ADC with a sampling speed of 20 MSPS is implemented in 0.18um CMOS. The ADC consumes 2.74 mW and achieves a peak SNDR of 74.33 dB which provides a FoM of 32.2 fJ/c-step with no calibration required.

A 7.5mW 35–70MHz 4th-order semi-passive charge-sharing band-pass filter with programmable bandwidth and 72dB stop-band rejection in 65nm CMOS

This paper proposes a highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that uses a semi-passive charge-sharing technique. It uses only switches, capacitors, digital circuitry for 3-phase non-overlapping clock generation and linearity-enhanced gm-stages. A 4th-order BPF prototype operating at 1.2GS/s sampling rate is implemented using a cascade of two independent biquads in a 65nm LPE CMOS. A tunable center frequency of 35-70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The in-band 1-dB compression point is -2.4dBm, and the in-band IIP3 is +9dBm. The filter prototype consumes 7.5mW from a 1.2V supply, and occupies an active area of 0.17mm2.

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers

A reference-free stochastic ADC is proposed by utilizing both spatial averaging and oversampling noise-shaping schemes. By implementing multiple VCO-based quantizers in parallel, stochastic spatial averaging for quantization errors is inherently obtained. In addition, 1st-order noise shaping of a VCO-based quantizer is achieved in an open-loop oversampling configuration. By resolving a faster conversion rate, this open-loop structure eliminates biasing, loop filter, sample-and-hold, and external reference, and it consists of only delay cells and digital logic. The proof-of-concept prototype which includes eight VCO-based quantizers and spatial averaging estimator is implemented in a 0.18 μm CMOS process, demonstrating 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, with 116 mW power consumption. Measurement results reveal that the eight channel stochastic ADC provides an average 9 dB SQNR improvement due to the spatial averaging.

A single OpAmp 2 nd -Order ΔΣ ADC with a double integrating quantizer

Time-to-digital converters are an attractive topology for quantization because they rely on mostly digital blocks that benefit from scaling of transistors. Time-to-digital converters inherently need a time-domain input, but the input to analog-to-digital converters is primarily in the voltage-domain. Therefore, a voltage-to-time converter is necessary to use time-to-digital converters in analog-to-digital converters. Previously, circuit modifications have allowed voltage-to-time converters to provide an extra order of quantization noise shaping when used within a delta-sigma analog-to-digital converter. This work proposes another method that allows the voltage-to-time converter to function as an integrator. When combined with previous methods, this allows for an extra two orders of noise shaping to result from the quantizer.

Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement

This paper presents a new dual-slope-based time-interleaved quantizer architecture. Time information between interleaved quantizer channels is utilized to perform time-domain delta modulation. This technique decouples the conversion rate of dual-slope quantizers from their input voltage amplitude without the need for extra timing phases or dedicated hardware.

Resistive correction of low output impedance high-speed current-steering DACs

Current-steering digital-to-analog converters are the architecture of choice in high-resolution high-speed applications. However, they are still affected by non-linearity that becomes worse with higher resolutions and higher speeds. This paper proposes a method of correction for one of the sources of non-linearity. This method is analyzed for its robustness to matching and absolute errors. The proposed method is analyzed using Monte-Carlo analysis, and then verified at the transistor level with simulations. A transistor level 12 bit 1GS/s digital-to-analog converter is simulated using a 65nm process. The transistor level simulations show a 20 dB improvement in spurious-free dynamic range.