Lisa F. Edge

Measurement of the band offsets between amorphous LaAlO3 and silicon

The conduction and valence band offsets between amorphous LaAlO3 and silicon have been determined from x-ray photoelectron spectroscopy measurements. These films, which are free of interfacial SiO2, were made by molecular-beam deposition. The band line-up is type I with measured band offsets of 1.8±0.2 eV for electrons and 3.2±0.1 eV for holes. The band offsets are independent of the doping concentration in the silicon substrate as well as the amorphous LaAlO3 film thickness. These amorphous LaAlO3 films have a bandgap of 6.2±0.1 eV.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at Ioff = 300 pA/µm, VDD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Suppression of subcutaneous oxidation during the deposition of amorphous lanthanum aluminate on silicon

Amorphous LaAlO3 thin films have been deposited by molecular beam deposition directly on silicon without detectable oxidation of the underlying substrate. We have studied these abrupt interfaces by Auger electron spectroscopy, high-resolution transmission electron microscopy, medium-energy ion scattering, transmission infrared absorption spectroscopy, and x-ray photoelectron spectroscopy. Together these techniques indicate that the films are fully oxidized and have less than 0.2 A of SiO2 at the interface between the amorphous LaAlO3 and silicon. These heterostructures are being investigated for alternative gate dielectric applications and provide an opportunity to control the interface between the silicon and the gate dielectric.

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

Outdiffusion of La and Al from amorphous LaAlO3 in direct contact with Si (001)

We have evaluated the thermal stability of Al2O3/LaAlO3/Si (001) stacks with atomic force microscopy, x-ray diffraction, transmission electron microscopy, and secondary ion mass spectrometry using a back side polishing approach. Crystallization of the amorphous LaAlO3 film was found to occur for rapid thermal anneals (RTA) above 935 °C for 20 s, in flowing N2. Penetration of Al and La into the underlying Si (001) is clearly observed for RTA at or above 950 °C for 20 s in flowing N2.

Conduction band-edge States associated with the removal of d-state degeneracies by the Jahn-Teller effect

X-ray absorption spectroscopy (XAS) is used to study band edge electronic structure of high-/spl kappa/ transition metal (TM) and trivalent lanthanide rare earth (RE) oxide gate dielectrics. The lowest conduction band d/sup */-states in TiO/sub 2/, ZrO/sub 2/ and HfO/sub 2/ are correlated with: 1) features in the O K/sub 1/ edge, and 2) transitions from occupied Ti 2p, Zr 3p and Hf 4p states to empty Ti 3d-, Zr 4d-, and Hf 5d-states, respectively. The relative energies of d-state features indicate that the respective optical bandgaps, E/sub opt/ (or equivalently, E/sub g/), and conduction band offset energy with respect to Si, E/sub B/, scale monotonically with the d-state energies of the TM/RE atoms. The multiplicity of d-state features in the Ti L/sub 2,3/ spectrum of TiO/sub 2/, and in the derivative of the O K/sub 1/ spectra for ZrO/sub 2/ and HfO/sub 2/ indicate a removal of d-state degeneracies that results from a static Jahn-Teller effect in these nanocrystalline thin film oxides. Similar removals of d-state degeneracies are demonstrated for complex TM/RE oxides including Zr and Hf titanates, and La, Gd and Dy scandates. Analysis of XAS and band edge spectra indicate an additional band edge state that is assigned Jahn-Teller distortions at internal grain boundaries. These band edges defect states are electronically active in photoconductivity (PC), internal photoemission (IPE), and act as bulk traps in metal oxide semiconductor (MOS) devices, contributing to asymmetries in tunneling and Frenkel-Poole transport that have important consequences for performance and reliability in advanced Si devices.

Electrical characterization of amorphous lanthanum aluminate thin films grown by molecular-beam deposition on silicon

Amorphous LaAlO3 thin films were deposited at room temperature directly on n-type and p-type Si (001) by molecular beam deposition. The dielectric properties of the stoichiometric amorphous LaAlO3 thin films deposited on silicon were determined through capacitance-voltage and current-voltage measurements. The electrical measurements indicate that the amorphous LaAlO3 thin films have a dielectric constant (K) of K=16±2. This is significantly lower than the K=24 of crystalline LaAlO3. The equivalent oxide thickness values range between 9.8 and 15.5A for films deposited on n-type silicon with physical thicknesses of 45–75A.

22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the worlds smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at VDD = 0.9V and VDD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths. Furthermore, cSiGe modulates device Vt, thus providing an additional knob to enable multi-Vt while maintaining undoped channels for all devices.