Qinghu Cui

Design and optimization of redistribution layer (RDL) on TSV interposer for high frequency applications

The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presented in this paper. BCB is selected as the passivation layer and the electroplated Cu is used as the metal layer. CYCLOTENE 3024–46 is utilized and it is deposited by spin-coating and soft cure at 210 °C in annealing oven for 40 minutes with N2 protection. Sputtered Ti/W/Cu and electron beam evaporated Ti/Cu on BCB have shown good adhesion. Daisy chain of the two metal layers and double layer of CPW are fabricated. The RDL of MSL and CPW are simulated by Ansoft HFSS. In condition of folded shape of RDL, multilayer of folded RDL gives the better performance than that of single layer and even has lower attenuation than straight line by optimization. Multilayer of RDL can also offset the insertion loss brought by TSV and has lower return loss. Multilayer of RDL with increasing width of metal line gradually from bottom to top is good for signal transmission and system reliability.

Design and process development of a stacked SRAM memory chip module with TSV interconnection

In this paper, a stacked SRAM chip module is presented and simulation results are demonstrated. A novel 3D integration process is presented and challenging issues are addressed. With this novel process, theres no need to do grinding/polishing of copper overburden after filling of TSV by copper electroplating. Copper microbumps will be formed directly on the active side in the filling of TSV by copper electroplating while the ones on the backside will be formed with backside releasing process. A test run is carried out with this novel process and a 4-layer stacked chip module is successfully fabricated.

Process development of multi-layer stacked chip module

In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.

Understanding effect of additives in copper electroplating filling for through silicon via

3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next generation integrated circuits. Copper electroplating is one of the key technologies to fabricate TSVs. In this paper, void-free TSV filling was achieved using methanesulfonic based electrolyte and mushroom-like copper overburden was used as bumps after tin deposition. Effect of additives and current density in copper electroplating nucleation and filling profile was investigated. An absorption-diffusion model was employed to explain the experimental results.

Electrical characterization of cylindrical and annular TSV for combined application thereof

In this paper, the potential application of combining cylindrical TSV and annular TSV into 3D integration was studied. First, the schematic fabrication process of cylindrical and annular TSV was proposed. Lumped equivalent circuit model of these different kinds of TSV structures from the physical configuration were studied and verified. Besides, 3D full wave electromagnetic (EM) simulations of cylindrical TSVs and annular TSVs were performed to verify the proposed lumped model of TSV.

Electrical characterization of integrated passive devices using thin film technology for 3D integration

With the development of 3D integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices (IPDs), including inductors, capacitors, and resistors, could dramatically save the footprint of the system, optimize the form factor, and improve the performance of radio frequency (RF) systems. In this paper, IPDs using thin film built-up technology are introduced, and the design and characterization of coplanar waveguides (CPWs), inductors, and capacitors are presented.

Effect of additives on copper electroplating profile for TSV filling

3D integration with TSVs is emerging as a promising technology for the next generation integrated circuits. TSV filling is a critical process in TSV fabrication and has direct effect on electrical performance of TSVs. In this paper, we mainly focus on effect of additives used in methanesulfonic based solution on copper electroplating filling. Numerical simulation based on an absorption-diffusion model has been carried out with electrochemical data. TSV filling experiment results with different additive concentrations are presented and void-free TSV filling has been achieved.

Design and fabrication of a TSV interposer for SRAM integration

TSV interposer provides a cost efficient solution way for 3D IC integration. In this paper, a TSV interposer technology is proposed for SRAM stacking. A simple fabrication process is developed for cost-sensitive application. The mushroomlike Cu/Sn bumps by copper overburden can be directly connected with other substrate, which eliminates a CMP planarization to improve the yield and reduce fabrication cost. The electrical and thermal-mechanical behaviors of the 3D system were analyzed. Preliminary fabrication results are demonstrated. The TSV interposer technology is promising for 3D SRAM integration.

Process development of a stacked chip module with TSV interconnection

In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, theres no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a test run is carried out and a four-layer of chip module is demonstrated.

Development of a through-stack-via integrated SRAM module

In this paper, a through-stack-via integration process for SRAM module was developed using wafer level pre-patterned BCB bonding. A SRAM module with a built-in decoder has been designed according to this integration process. TSVs passed through all stacked SRAM chips and common signals, including address bus, data bus, power, write and read control, were connected to the same TSV using RDL. The chip select signals are individually connected to the built-in decoder. RDL was fabricated using lift-off process prior to wafer bonding and via filling. Double-layer spin coating technology was employed to prevent photoresist residues left in TSVs. With pre-patterned BCB adhesive bonding, a bottom-up TSV filling features as the last step, which eliminates the traditional solder bumping, flip chip bonding and underfill filling processes. Preliminary results have shown that this process is promising for integration of memory chips with similar layout.