C.T. Chuang

A submicrometer high-performance bipolar technology

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated.<<ETX>>

A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the conventional ECL gate. The speed/power advantages of the circuit have been demonstrated in a double-poly, trench-isolated, self-aligned bipolar process with 0.8- mu m (mask) emitter width. Unloaded gate delays of 21 ps at 4.1 mW/gate, 23 ps at 2.1 mW/gate, and 35 ps at 1.1 mW/gate have been measured. >

On the punchthrough characteristics of advanced self-aligned bipolar transistors

This paper presents a detailed two-dimensional numerical simulation study on the punchthrough characteristics of advanced self-aligned bipolar transistors utilizing a sidewall spacer technology. Particular emphasis is placed on the effect of the sidewall spacer thickness. Perimeter punchthrough due to insufficient extrinsic-intrinsic base overlap is shown to be a major concern. The tradeoff between the punchthrough current and the maximum surface electric field in the depletion region of the extrinsic base-emitter junction, which relates closely to the perimeter tunneling current, is discussed.

High-speed low-power direct-coupled complementary push-pull ECL circuit

A high-speed, low-power, AC-coupled complementary push-pull ECL (AC-PP-ECL) circuit is presented. The circuit utilizes two capacitors to couple a transient voltage pulse from the common-emitter node of the switching transistors to the bases of a pair of complementary p-n-p/n-p-n push-pull transistors to provide a large transient current during switching. In addition to a reduction of the power consumption and improvement in the pull-up and pull-down capability of the output stage, the circuit scheme completely decouples the collector load resistor R/sub c/ from the delay path, thus allowing a very small switching current to be used for the logic (current switch) stage without degrading the performance. Based on a 0.8- mu m double-poly self-aligned complementary bipolar process at a power consumption of 0.5 mW/gate, the circuit offers 2.1* improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed. >

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.

Circuit design techniques for the high-performance CMOS IBM S/390 parallel enterprise server G4 microprocessor

This paper describes the circuit design techniques used for the IBM S/390® Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approaches reduced risk and shortened the design time. The use of timing-driven synthesis/placement methodologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits facilitated the balancing of design time and performance return. The use of robust PLL design, floorplanning, and clock distribution minimized clock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innovations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.

An advanced bipolar transistor with self-aligned ion-planted base and W/poly emitter

The fabrication, device profile, and electrical characteristics of an advanced bipolar transistor with an LDD-like self-aligned lateral profile are discussed. An ion-implanted extrinsic base with a low sheet resistance of 55 Omega /square and a junction depth of 0.35 mu m is obtained using rapid thermal annealing. The extrinsic base and emitter are separated by a temporary submicrometer sidewall spacer, which is subsequently removed to maintain a planar surface during the emitter-active-base formation process. The emitter is contacted by a W-TiN-n/sup +/ polysilicon stack with a sheet resistance of 1 Omega /square. As a result of the planarity of the surface during the profile formation for the active region and the decoupling of the structural process from the thin base process, an active base width of 105 nm is obtained. >

A 27 GHz 20 ps PNP technology

Summary form only given. A high-performance double-poly p-n-p technology, with features allowing it to be easily integrated into a more general complementary bipolar process, is described. These advanced p-n-p transistors have 80-nm-wide ion-implanted bases and optimized emitter and collector dopant profiles and are fabricated on a thin p-type epilaver in order to achieve high collector current driving capability. The devices have a measured cutoff frequency of 27 GHz, making them the fastest silicon p-n-p bipolar transistors reported to date. Experimental results on the device characteristics are presented.<<ETX>>

A 23 ps/2.1 mW ECL gate

Simulated output waveforms at 0.1, 0.3 and, 0.6-pF loading of a design optimized for a 0.3-pF nominal load are shown. An AC-coupled APD ECL (active-pull-down emitter-coupled-logic) gate with significantly improved gate delay in the low-power (1-2 mW) regime is described. Unloaded gate delays of 23 and 35 ps at 2.1 and 1.1-mW/gate power, respectively, were demonstrated in a bipolar technology using a double-poly, self-aligned process with emitter width of 0.8 mu m (mask). The device cross-section is presented along with an SEM (scanning electron microscopy) micrograph of the basic gate used in the ring oscillator.<<ETX>>

High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage

The design of an ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array applications is presented. The circuit features an AC-coupled dynamic current source to improve the power-delay of the logic stage (current switch). A self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8- mu m double-poly, self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.62* (1.90*) improvement in the speed (load driving capability) of a loaded gate compared with the conventional ECL circuit. >