R.F.M. Roes

Dopant profile engineering of advanced Si MOSFET’s using ion implantation

Abstract Ion implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET’s. After defining the transistor configuration, SR profiles were formed by dopant implantation through the polycrystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation.

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 /spl mu/m CMOS low-voltage applications

We have studied an aggressive lateral MOS channel profiling combined with gate work function engineering for sub-0.13 /spl mu/m generation PMOSFETs oriented for low-voltage operation. In this scheme, the Ge fraction in the poly-SiGe gate was used to control threshold voltage V/sub T/, while short channel effects (SCE) were completely suppressed down to 100 nm gate lengths by heavily doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no V/sub T/ roll-off behaviour, and 67 mV/dec sub-V/sub T/ voltage swing. The low channel doping leads to significant improvements in the channel mobility and parasitic capacitances, resulting in excellent I/sub on//I/sub off/ behaviour and record ring oscillator delays for low-voltage operation. Process variation analysis confirmed the high manufacturing potential for the approach suggested. The approach can be extended to n-type devices with a suitable choice of gate work function.

Making 50 nm transistors with 248 nm lithography

Using a novel phase-shift mask, 50 nm resolution has been achieved with conventional 248 nm lithography. The addition of so-called scattering bars enables within-die control of linewidths from 250 to 50 nm. Using 200 nm thick resist layers combined with hard mask processing, transistors with gate-lengths down to 50 nm have been fabricated. Well controlled device performance is achieved by optimizing offset spacers and pocket implants.