R. Maas

EUV resist performance: current assessment for sub-22-nm half-pitch patterning on NXE:3300

The major challenge for EUV resists at 22 nm half-pitch and below continues to be simultaneously achieving resolution, sensitivity, and line-width roughness (LWR) targets. An ongoing micro-exposure tool (MET) based evaluation of leading resists throughout 2011 shows that incremental progress toward meeting requirements continues apace, with best-of-breed candidates now capable of limiting 19 nm half-pitch resolution at sensitivities near or below 20 mJ/cm2 and LWR below 4 nm 3σ through process window. Evaluation of a selection of leading resists using an ASML NXE:3100 2nd generation full-field exposure tool demonstrates key performance improvements vs. the previous process-of- record (POR) setup resist including enhanced process window at 22 nm half-pitch and better contact hole uniformity. Champion limiting resolution performance for chemically amplified resists at a relaxed sensitivity specification has advanced to 16 nm half-pitch for both MET and full-field exposures.

Challenge toward breakage of RLS trade-off for EUV lithography by Photosensitized Chemically Amplified Resist (PSCAR) with flood exposure

This paper proposes a promising approach to break the resolution (R), line-edge-roughness (LER), and sensitivity (S) trade-off (RLS trade-off) relationships that limit the ultimate lithographic performance of standard chemically amplified resists (CAR). This is accomplished in a process that uses a Photosensitized Chemically Amplified Resist (PSCAR) in combination with a flood-exposure in an in-line track connected to a pattern exposure tool. PSCAR is a modified CAR which contains a photosensitizer precursor (PP) in addition to other standard CAR components such as a protected polymer, a photo acid generator (PAG) and a quencher. In this paper, the PSCAR concept and the required conditions in resist formulation are carefully explained. In the PSCAR process, the sensitivity improvement is accomplished by PAG decomposition to selectively generate more acid at the pattern exposed areas during the flood exposure. The selective photosensitization happens through the excitation of the photosensitizer (PS) generated by the deprotection of the PP at the pattern exposed areas. A higher resist chemical gradient which leads to an improved resolution and lower LER values is also predicted using the PSCAR simulator. In the PSCAR process, the improved chemical gradient can be realized by dual acid quenching steps with the help of increased quencher concentration. Acid quenching first happens simultaneously with acid catalytic PP to PS reactions. As a result, a sharpened PS latent image is created in the PSCAR. This image is subsequently excited by the flood exposure creating additional acid products at the pattern exposed areas only. Much the same as in the standard CAR system, unnecessary acid present in the non-pattern exposed areas can be neutralized by the remaining quencher to therefore produce sharper acid latent images. EUV exposure results down to 15 nm half pitch (HP) line/space (L/S) patterns using a PSCAR resist indicate that the use of PSCAR has the potential to improve the sensitivity of the system while simultaneously improving the line-width-roughness (LWR) with added quencher and flood exposure doses. In addition, improved across-wafer critical dimension uniformity (CDU) is realized by the use of a PSCAR in combination with a flood exposure using pre α UV exposure module.

Novel high sensitivity EUV photoresist for sub-7nm node

Extreme ultraviolet lithography (EUVL) has been recognized as the most promising candidate for the manufacture of semiconductor devices for the 7 nm node and beyond. A key point in the successful introduction of EUV lithography in high volume manufacture (HVM) is the effective EUV dose utilization while simultaneously realizing ultra-high resolution and low line edge roughness (LER). Here we show EUV resist sensitivity improvement with the use of a photosensitized chemically amplified resist PSCARTM system. The evaluation of this new chemically amplified resist (CAR) as performed using EUV interference lithography (EUV-IL) is described and the fundamentals are discussed.

Wafer edge polishing process for defect reduction during immersion lithography

The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.

Improvements in process performance for immersion technology high volume manufacturing

Through collaborative efforts ASML and TEL are continuously improving the process performance for the LITHIUS Pro -i/ TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML have investigated the CDU and defectivity performance for the 45nm node with high through put processing. CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from the multi-module processing on the LITHIUS Pro -i, using a topcoat resist process. For increased productivity, a new bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface. However, with the necessity of double patterning for at least the next technology node, more stringent requirements are necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity. In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are investigated to increase the customers productivity and yield for whichever double patterning scheme is utilized. Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated. Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.

Investigation of processing performance and requirements for next generation lithography cluster tools

In this paper we summarize our investigations into processing capability on the CLEAN TRACKTM LITHIUS ProTM -i & TWINSCANTM NXT:1950i litho cluster. Process performance with regards to critical dimension (CD) uniformity and defectivity are investigated to confirm adherence to ITRS1 roadmaps specifications. Additionally, a study of wafer backside particle contamination is performed to understand the implications towards processing. As wafer stage chuck cleaning on the scanner will require considerable down time, this study is necessary to understand the requirements for manufacturability. Previous work from our collaboration succeeded in a processing improvement of over 80% in across wafer CD variation by implementing the newest post exposure bake (PEB) plate design2 and optimized developer process. With regards to defectivity, the use of the advanced defect reduction (ADR) process with an optimized bevel cut of the resist allowed the use of a high contact angle material process which is required for optimal immersion hood performance. In this work, further optimization of the process with consideration of the design concept of the TWINSCANTM NXT:1950i and hardware modifications on the CLEAN TRACKTM LITHIUS ProTM -i will be performed. From this investigation, it is expected to understand the process capability of 38nm CD uniformity using novel developer hardware. Additionally, the defectivity challenges for processing with higher scan speeds in combination with the hydrophobicity of the coating materials and edge cut strategy will be clarified. Initial evaluation results are analyzed to understand the correlation of various types and densities of contaminates on the backside of the wafer to the formation of wafer stage chuck focus spots (FS). Focus spots are a localized irregular focus and leveling height.

Evaluation of next generation hardware for lithography processing

This work is the summary of improvements in processing capability implemented and tested on the LITHIUS ProTM -i / TWINSCANTM XT:1950Hi litho cluster installed at ASMLs development clean room at Veldhoven, the Netherlands. Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to ITRS roadmaps specifications. Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect reduction hardware with the novel immersion hood design will be tested. For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of ASMLs new immersion hood and TELs defect reduction hardware were evaluated. The new immersion hood performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process. The high contact angle materials could be shown to be successfully processed by using TELs Advanced Defect Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.

Defectivity process optimization on immersion topcoat less resist stacks

Demand for Immersion topcoat-less resist processes is being driven by the desire to reduce the cost per wafer pass. Two key characteristics, required by high speed immersion scanners, of topcoat-less resist are high receding contact angle and low leaching rates. The extremely hydrophobic surface required by the scanner provides significant challenges to the remaining processing steps, especially (developer) process related defects: pattern collapse and hydrophobic residuals. Recent developments in materials and processing techniques have led to very promising results. In this paper the following will be presented: Defectivity results on 45nm L/S of several topcoat-less resists, including the effects of optimized track rinse recipes. Results of a fundamental study on static contact angles changes of different topcoat-less resists after each track process step to identify where in the process issues originate. Imaging and defectivity results of 38nm L/S using the topcoat-less champion resist are presented. These results illustrate the capability of the ASML TWINSCAN XT:1900i / Sokudo RF3i litho cluster of printing 38 nm L/S in a single exposure .

Process manufacturability evaluation for next generation immersion technology node

In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process manufacturability performance of the CLEAN TRACKTM LITHIUS ProTM-i/ TWINSCANTM XT:1900Gi lithocluster at the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUSTM i+/TWINSCAN XT:1700i. 1 In this work, process performance with regards to critical dimension uniformity and defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.