R. Versari

Experimental study of hot-carrier effects in LDMOS transistors

Hot-carrier currents and the induced degradation mechanisms in lateral double-diffused MOS (LDMOS) transistors for smart power applications are investigated in detail. Three different regions within the device where significant hot-carrier generation can occur depending on bias as well as device technological parameters have been identified. Guidelines to suppress the degradation mechanisms involving the two lightly doped regions of the device not overlapped by the gate electrode, responsible for the stronger device degradation, are provided. Devices optimized according to the given guidelines have been fabricated and demonstrate a strong hot carrier resistance.

Hot-carrier reliability in submicrometer LDMOS transistors

This paper provides a physical basis for the experimentally determined hot-electron-limited safe operating area of submicrometer LDMOS transistors under static bias conditions. The physical interpretation of the device behavior is based on the analysis of the bias-dependent gate and substrate currents and of the relative induced degradation.

Characterization of polysilicon-gate depletion in MOS structures

This paper presents a new technique to characterize the depletion capacitance and (active) impurity concentration of gate polysilicon in MOS transistors. The method has been validated by means of 2-D simulation; experimental results obtained with state-of-the-art n-channel 0.5 micrometer transistors are presented.

Fast tunneling programming of nonvolatile memories

This work investigates the possibility of programming nonvolatile memories in the ns time scale, for possible replacement of DRAMs, at least in special applications where low-power requirements do not allow frequent data refreshing. The study demonstrates the possibility of using high voltage tunneling pulses to achieve program times significantly shorter than 100 ns with acceptable oxide damage.

Fast programming/erasing of thin-oxide EEPROMs

This work demonstrates that conventional thin-oxide EEPROM cells can be programmed (erased) in the nanosecond time scale with voltages lower than 18 V and still feature data retention times of the order of a few hours after 100 K program/erase (P/E) cycles. Our results suggest that thin-oxide nonvolatile (NV) memory devices can be suitable for fast read/write dynamic applications, at least when high cycling endurance is not a primary specification.

Light emission from MOS tunnel diodes

Special MOS tunneling structures which, avoiding the obscuring effects of the polysilicon layer, exhibit excellent light emission characteristics, have been fabricated and tested. For the first time, it is shown that the experimental photon energy distributions of MOS tunnel diodes biased in the Fowler-Nordheim regime exhibit a peak at about 1.6 eV, likely due to hot-carrier radiative recombination phenomena.

MOSFET's negative transconductance at room temperature

Negative transconductance is reported for the first time at T=300 K for NMOS transistors fabricated with different technologies and oxide thickness in the 3-20 nm range. The effects of drain bias, channel length, oxide thickness as well as substrate doping and bias on the phenomenon are investigated. The results are interpreted in terms of surface-roughness limited mobility, and parameters for mobility modeling at high effective fields are extracted.

Optimized programming of multilevel flash EEPROMs

The trade-off between speed and dispersion of programmed threshold voltages is investigated in 0.25 /spl mu/m flash memory technology. It is shown that ramped gate programming provides tighter distributions of programmed threshold voltages than its conventional box-waveform counterpart, allowing a larger number of bits per second to be written. In particular, at low programming speed, ramped gate programming is shown to allow four level schemes without program and verify operations, with a program bandwidth potentially approaching 30 Mbits/s in the conventional one-bit-per-cell scheme (and correspondingly higher values in the multi-level case). Instead, sixteen level schemes without program and verify do not seem practically feasible.

Bandwidth optimization of flash memories with the RGP technique

A simple expression for the number of bits that can be programmed per unit time (bandwidth or BW) in flash memories with the ramped gate programming (RGP) technique is used to optimize memory BW and derive design curves. Preliminary experimental results obtained with common-ground NOR flash memory arrays realized with 0.25 /spl mu/m technology show that memory BW can: (1) exceed of 10 Mb/s with optimized cell programming and (2) be negatively affected by device scaling.

Fowler Nordheim induced light emission from MOS diodes

Light emission from MOS tunnel diodes biased in the Fowler-Nordheim regime has been investigated by using especially designed test structures which avoid the obscuring effect of the poly-Si layer, thus allowing an efficient light emission from the Si substrate. The measured photon energy distribution of the emitted light is consistent with a hot carrier radiation model.