Massimo Lanzoni

Nonvolatile multilevel memories for digital applications

When thinking of semiconductor memories, it comes naturally to associate stored bits and memory cells with a one-to-one relationship. That, however, is not really a must nor necessarily the most convenient solution for data storage, since using analog signals and digital-to-analog (D/A) as well as analog-to digital (A/D) conversions a large number of bits could be memorized in a single cell, although, of course, the use of analog signals presents all drawbacks of signal-to-noise ratio that are so well known in electronics. In fact, the real question in this sense concerns the number of bits used for the A/D and D/A conversions, since the conventional (fully) digital case can be seen as the simplest realization of a general approach tending to infinitely precise analog storage (i.e. an infinite number of stored bits per cell) at the other extreme. Naturally, in the real world the conflicting aspects of density (measured in bits per cell) and noise immunity (in a general sense) should be traded off one against the other looking for optimum use of silicon area, of course depending on technology, architectures, circuits and reliability. From this point of view it is obvious that the fully digital approach based on the one-bit one-cell concept does not represent necessarily the best solution. Recently, this general question has assumed real and practical significance for nonvolatile memories, since devices storing two bits per cell are now being introduced on the market. At the same time, in a number of research labs a significant effort is currently being dedicated to the study of the limits and practical convenience of storage density considering the current state of the art in technology and circuit designs. This problem, however, presents a number of interacting aspects concerning cell concept, programming and reading schemes, and architectures and reliability that are of interest well beyond the field of nonvolatile memories, because they are ultimately dealing with the basic question of analog versus digital signals. In this contrast, the present paper considers the question of multilevel nonvolatile memories in all its interacting aspects, analyzing both the current state of the art and the future possibilities.

A novel approach to controlled programming of tunnel-based floating-gate MOSFETs

This paper presents a new approach to obtain automatic and accurate control of the threshold voltage of floating-gate MOSFETs programmable by means of tunneling current. The proposed method avoids using a series of partial write/erase operations followed by measurements and adjustment steps, thus achieving a significant advantage in terms of programming time for the same accuracy. The simplicity of the proposed method and its inherent speed make it ideal in a wide range of possible applications. >

Program schemes for multilevel flash memories

This paper presents a synthetic overview of multilevel (ML) flash memory program methods. The problem of increasing program time with the number of bits stored in each cell is discussed and methods based on both channel hot electrons (CHE) and Fowler-Nordheim tunneling (FNT) are discussed. In the case of CHE, the use of an increasing voltage rather than a constant one on the control gate (CG) leads to narrower threshold voltage distributions and smaller current absorption, with positive effects on the degree of parallelism and program throughput. As for FNT, much faster programming than that commonly used today can be done using high CG voltages without producing intolerable degradation of cell reliability.

Temperature dependence of Fowler-Nordheim injection from accumulated n-type silicon into silicon dioxide

The temperature dependence of the Fowler-Nordheim (F-N) injection of electrons from accumulated n-Si to SiO/sub 2/ is analyzed. The F-N current-voltage characteristics of thin-oxide (8.5 nm)

Advanced electrical-level modeling of EEPROM cells

Conventional modeling of floating-gate electrically erasable programmable read-only memory (EEPROM) cells is shown to be inadequate to correctly evaluate the tunnel current flowing through the MOS injector during programming, essentially because of relevant quantum phenomena taking place at the cathode semiconductor-oxide interface. An electrical-level model incorporating numerical analysis of such effects is developed and discussed. The model is validated by comparing results of the simulations with experimental data obtained with EEPROM cells. The model of the MOS injector has been implemented in the circuit simulator SPICE. >

Automatic and continuous offset compensation of MOS operational amplifiers using floating-gate transistors

This paper presents a new approach that exploits floating-gate MOS transistors and a feedback control loop to automatically compensate the offset of MOS operational amplifiers in a continuous manner that substantially improves the state of the art in the field. The proposed method can be repeatedly used to compensate the effects of environmental and device modifications, while the possibility to accurately program an arbitrary value of the offset can be exploited to realize high performance and/or programmable comparators and A/D converters.

An experimental study of testing techniques for bridging faults in CMOS ICs

An experimental analysis of discrete Fourier transform (DFT) techniques used to detect the presence of faulty resistive paths throughout CMOS ICs is presented. Current monitoring, delay fault testing, and new design-for-testability (DFT) techniques are compared by means of a chip designed ad hoc that allows the presence of resistive bridgings within standard functional blocks to be simulated via hardware. The results suggest that specific DFT techniques offer considerable advantages over more conventional approaches. >

Investigation of hot electron luminescence in silicon by means of dual-gate MOSFET's

This paper contributes to the experimental analysis of hot-carrier induced photon emission from silicon devices by reporting integral and spectrally resolved light intensity measurements on dual gate n-MOSFETs. Exploiting the peculiar possibility, typical of this device structure, to move the light emission point between regions featuring significantly different doping concentrations, new insight is obtained on the contribution of radiative recombinations and ionized impurity assisted intraband transitions to the emitted light intensity.

Optimized programming of multilevel flash EEPROMs

The trade-off between speed and dispersion of programmed threshold voltages is investigated in 0.25 /spl mu/m flash memory technology. It is shown that ramped gate programming provides tighter distributions of programmed threshold voltages than its conventional box-waveform counterpart, allowing a larger number of bits per second to be written. In particular, at low programming speed, ramped gate programming is shown to allow four level schemes without program and verify operations, with a program bandwidth potentially approaching 30 Mbits/s in the conventional one-bit-per-cell scheme (and correspondingly higher values in the multi-level case). Instead, sixteen level schemes without program and verify do not seem practically feasible.

Experimental characterization of circuits for controlled programming of floating-gate MOSFET's

This paper presents the results of measurements performed on test structures implementing circuits for controlled erase of floating gate MOSFETs. The obtained results show that, with cells fabricated using standard technology, the obtained performance is sufficiently good to allow use in analog applications. The circuit has been demonstrated to be robust with respect to variations of the programming pulse characteristics and to partially compensate cell aging effects on the threshold window. This latter feature is particularly interesting for digital applications because it allows the reduction of the window margin, thus improving memory endurance. >