Rachel Gordin

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices

This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in D. Goren et al. (2002), into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T-line) devices for the critical interconnects, which is expanded to include coplanar structures while considering the silicon substrate effect. The generalized methodology contains treatment of the crossing line effects at the various design stages, including two way interactions between the post layout extraction tool and the T-line devices. The T-line device models are passive by construction, easily migratable among design environments, and allow for both time and frequency domain simulations. These models are verified by S-parameter measurements up to 110GHz, as well as by EM solver results. It is experimentally shown that the effect of properly designed discontinuities is negligible in most practical cases. The basic on-chip T-line methodology is being used extensively for numerous high-speed designs.

An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach

This paper presents an on-chip, interconnect-aware methodology for high-speed analog and mixed signal (AMS) design which enables early incorporation of on-chip transmission line (T-line) components into AMS design flow. The proposed solution is based on a set of parameterized T-line structures, which include single and two coupled microstrip lines with optional side shielding, accompanied by compact true transient models. The models account for frequency dependent skin and proximity effects, while maintaining passivity requirements due to their pure RLC nature. The signal bandwidth supported by the models covers a range from DC to 100 GHz. The models are currently verified in terms of S-parameter data against hardware (up to 40 GHz) and against EM solver (up to 100 GHz). This methodology has already been used for several designs implemented in SiGe (silicon-germanium) BiCMOS technology.

Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology

Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4s) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.

Design and Modeling Methodology of Vertical Interconnects for 3DI Applications

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm.

Study of the compound of properties of percolating and neck-based thermal underfills

Percolating and neck-based thermal underfills with significant improvements in thermal conductivity compared with capillary underfills are currently under development. They could be applied between dies to improve the heat dissipation through a 3D chip stack. In this parametric study, we provide insights into the thermal, mechanical, thermo-mechanical and electrical properties achievable by this new composite material class. The primary objective of the investigation is the linear buckling phase of monodisperse spherical filler particles confined between two parallel plates with a fill fraction range of 48.7% to 61.3% as observed by experiment. The introduction of necks between the point contacts of the filler particles had the most significant impact on the composite effective material properties, resulting in an increase in thermal conductivity, stiffness and a drop in the thermal expansion coefficient. The high stiffness could cause delamination of the underfill in chip corners because of high shear forces and hence may have to be mitigated. Finally, two design points for the composite were proposed, respecting the target values for the percolating and neck-based thermal underfill, with a predicted effective thermal conductivity of 1.9 and 3.6 W/m-K.

TSV multi-signal connection compact modeling

This paper presents wideband circuit level compact models of through-silicon via (TSV) multi-signal connections within an array. The models were developed for time and frequency domain characterization of periodic TSV array patterns, including crosstalk evaluation. A frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as the skin and proximity effects. The models were verified by EM simulations up to 30 GHz.