Shlomo Shlafman

Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology

Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4s) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.

Design and Modeling Methodology of Vertical Interconnects for 3DI Applications

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm.

A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI

The gain/linearity trade-off is exploited to achieve the best linearity performance of a mm-Wave down-conversion system. The achieved linearity (IIP3) for the whole down-conversion chain is better than 11.06dBm for 5.8dB gain at 60GHz. Gain can be adjusted from -15dB to 11dB in 1dB steps depending on the signal level. By adjusting phase matching at RF input and the common-mode impedance of the mixer with a variable transmission line, the input phase imbalance can be corrected and the second-order distortion (HD2) can be reduced. The LO/RF isolation is 43dB and the LO/IF isolation is better than 82dB. The down-converter occupies 1.38mm2 in 32nm CMOS SOI and consumes 19.2mW from 1V supply. The power consumption of the mixer itself is 4mW @ 1V supply.

Variable Delay Transmission Lines in advanced CMOS SOI technology

Variable (Delay) Transmission Lines (VTL) offer digital tuning of fabricated transmission lines to compensate for process variation in active and passive devices of RF silicon design enabling self-healing and post-production circuit tuning. A novel compact semi-analytic single ended VTL model, enabling accurate RFIC circuit level simulation to enhance design flow, was developed. VTL structures were fabricated and measured in IBM 32nm CMOS SOI technology. The 30,50,80 Ohm VTL structures, consisting of metal crossing lines between the signal line and ground plane that are connected to ground through CMOS switches, exhibit over 11%, 15%, 18% delay tuning range respectively with low insertion loss and good agreement between measured results and developed model simulations.

TSV multi-signal connection compact modeling

This paper presents wideband circuit level compact models of through-silicon via (TSV) multi-signal connections within an array. The models were developed for time and frequency domain characterization of periodic TSV array patterns, including crosstalk evaluation. A frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as the skin and proximity effects. The models were verified by EM simulations up to 30 GHz.

On-chip CMOS coplanar transmission line measurements and model verification up to 50 GHz

The results show good agreement between de-embedded measurement and T- line coplanar model in both S-parameters and in Zo representation. In all cases the results of the T-line coplanar model are very close to the corresponding results of the EM solver. The RC model deviates significantly in the frequency domain from the T-line coplanar model results - both in S- parameters and in -Zo representation. The design impact of these deviations depends on the design niche (eg. digital vs. RF), and for a given design niche it may apply only to a given subset of critical wires (eg. clock line, high speed signal line etc.). The criticality of a given wire depends also on the wire length, and the on-chip effective bandwidth (rise time in digital or frequency in RF). For digital designs, the criteria for using a model that includes inductive effects (instead of RC model) was given and discussed previously.The considerations of designing the RF launching structures have been discussed. We have found that a robust optimal design of the RF launching structure allows for the usage of very simple de-embedding techniques up to relatively high frequencies.