C. S. Tan

Technology, performance, and computer-aided design of three-dimensional integrated circuits

We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.

Morphology and Bond Strength of Copper Wafer Bonding

The morphology and bond strength of copper-bonded wafer pairs prepared under different bonding/annealing temperatures and durations are presented. The interfacial morphology was examined by transmission electron microscopy while the bond strength was examined from a diesaw test. Physical mechanisms explaining the different roles of postbonding anneals at temperatures above and below 300°C are discussed. A map summarizing these results provides a useful reference on process conditions suitable for actual microelectronics fabrication and three-dimensional integrated circuits based on Cu wafer bonding.

Microstructure evolution and abnormal grain growth during copper wafer bonding

Evolution of microstructure morphologies and grain orientations of Cu–Cu bonded wafers during bonding and annealing were studied by means of transmission electron microscopy, electron diffraction, and x-ray diffraction. The bonded Cu grain structure reaches steady state after post-bonding anneal. An abnormal (220) grain growth was observed during the initial bonding process. Upon annealing, the preferred grain orientation of the whole film shifts from (111) to (220). The effects of yielding and energy minimization are possible reasons for the evolution of the preferred grain orientation.

Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology

A novel test structure for contact resistance measurement of bonded copper interconnects in three-dimensional integration technology is proposed and fabricated. This test structure requires a simple fabrication process and eliminates the possibility of measurement errors due to misalignment during bonding. Specific contact resistances of bonding interfaces with different interconnect sizes of approximately 10/sup -8/ /spl Omega/-cm/sup 2/ are measured. A reduction in specific contact resistance is obtained by longer anneal time. The specific contact resistance of bonded interconnects with longer anneal time does not change with interconnect sizes.

Low-temperature thermal oxide to plasma-enhanced chemical vapor deposition oxide wafer bonding for thin-film transfer application

Low-temperature direct plasma-enhanced chemical vapor deposition (PECVD) oxide to thermal oxide bonding is described. The PECVD oxide is densified at 350 °C and chemical-mechanically polished to obtain reasonably smooth surface for bonding. The PECVD oxide wafer is bonded to the thermal oxide wafer at room temperature after piranha clean that leaves the wafer surfaces hydrophilic. A postbonding anneal at 300 °C completes the bonding. A void-free bonding interface is observed from infrared imaging and the bonding strength is estimated to be 432 mJ/m2. This bonding method can be used in a variety of applications, including three-dimensional integration.

Bonding parameters of blanket copper wafer bonding

A reliable copper wafer bonding process condition, which provides strong bonding at low bonding temperature with a short bonding duration and does not affect the device structure, is desirable for future three-dimensional (3-D) integration applications. In this review paper, the effects of different process parameters on the quality of blanket copper wafer bonding are reviewed and summarized. An overall view of copper wafer bonding for different bonding parameters, including pressure, temperature, duration, clean techniques, and anneal option, can be established. To achieve excellent copper wafer bonding results, 400°C bonding for 30 min. followed by 30 min. nitrogen anneal or 350°C bonding for 30 min. followed by 60 min. anneal bonding is necessary. In addition, by meeting the process requirements of future integrated circuit (IC) processes, the best bonding condition for 3-D integration can be determined.

Abnormal contact resistance reduction of bonded copper interconnects in three-dimensional integration during current stressing

Bonded copper interconnects were stressed with current to measure the specific contact resistance. For bonded copper interconnects without a prebonding HCl clean, the corresponding specific contact resistance did not change while increasing the stress current. However, for some interconnects with the prebonding HCl clean, an abnormal contact resistance reduction was observed during the increase of the stress current. The rise of temperature at the bonding interface area due to Joule heating under high current density may have caused the decrease of contact resistance. This behavior may be one option for quality enhancement in 3D integration at low temperature.

Observation of interfacial void formation in bonded copper layers

Silicon wafers are bonded using copper (Cu) as the bonding medium and annealed to enhance the bonding strength at temperatures ranging from 300to400°C. The original bonding interface disappears and the Cu layers merge to form a single homogeneous layer. Cross-section transmission electron microscopy reveals a number of voids at the original bonding interface. It is observed that the size of these interfacial voids increases with bonding temperature. Thermal stress relaxation is proposed as the cause for interfacial void formation in the bonded Cu layers.

Low-Temperature Direct CVD Oxides to Thermal Oxide Wafer Bonding in Silicon Layer Transfer

The bonding strength of low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition (PECVD) oxides to thermal oxide is studied. Prior to bonding, all CVD oxide wafers are subjected to careful surface preparation including densification, chemical-mechanical polishing, activation, and post-bond annealing to ensure high-quality bonding. All wafers show surface roughness and wafer bow suitable for bonding after the surface preparations. It is found that bonding strength increases upon annealing and saturates beyond 2 h of annealing for the temperature range of 200-300°C. Tetraethyl orthosilicate source PECVD oxide is found to exhibit suitable bonding properties and can be used in applications such as silicon layer transfer.

Process development and bonding quality investigations of silicon layer stacking based on copper wafer bonding

Process development of silicon layer stacking based on copper wafer bonding, grind-back, and etch-back was applied to demonstrate a strong four-layer-stack structure. Bonded copper layers in this structure became homogeneous layers and did not show original bonding interfaces. This process can be used in three-dimensional integrated circuit applications. Voids and total bonded area after each layer stacking were investigated for the bonding quality after each layer stacking. Large wafer bows from high residual stresses result in the structure failure at the stacking of a high number of layers.