Rafaella Fiorelli

Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors

In this paper, series-parallel (SP) current-division will be employed for the design of very low transconductance OTAs. From the theory and measurements, it will be shown that SP mirrors allow the division of currents with division factors of thousands, without reducing matching or noise performance. SP mirrors will be applied to the design of OTAs ranging from 33 pS to a few nS, with up to 1 V linear range, consuming in the order of 100nW, and with a reduced area. An integrated 3.3-s time-constant integrator will also be presented. Several design concerns will be studied: linearity, offset, noise, and leakages, as well as layout techniques. A final comparative analysis concludes that SP association of transistors allows the design of very efficient transconductors, for demanding applications in the field of implantable electronics, among others

LC-VCO Design Optimization Methodology Based on the

In this paper, an LC voltage-controlled oscillator (LC VCO) design optimization methodology based on the gm/ID tech nique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the com promises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier.

g_m/I_D

In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.

Ratio for Nanometer CMOS Technologies

A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented. The circuit is designed and optimized to work in a ZigBee receiver. Since this is a low power consumption standard, a single-ended LNA is preferred over a fully-differential topology because it leads to lower cost in area and power consumption. Also, moderate and weak inversions regions were selected for the operation of the principal transistors. The front-end prototype has been implemented in a 90 nm RF process and occupies a chip area of 0.74 mm2 including on-chip inductors. Very competitive results are observed: a maximum conversion gain (CG) of 30 dB, a DSB noise figure of 7.5 dB, a maximum IIP3 of −12.8 dBm and IIP2 of 14.4 dBm while it consumes 4.7 mW from a 1.2 V supply.

MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs

This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS

In this paper the series-parallel association of transistors applied to current mirrors with a non-unity copy factor is studied with regard to mismatch. This technique has been demonstrated to be a valuable tool in the design of low-offset oriented analog circuits. Some measurements are presented as well as a minimum offset design.

Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs

A tool that explores the design space of basic RF circuit blocks is presented. The tool takes advantage of the application of an MOS transistor model continuous in all inversion levels (weak to strong inversion). The performance of the circuit is analyzed in the ID -gm/ID plane. The tool shows the existence of an inversion level that provides an optimum in the power consumption for a given gain and frequency. Examples are presented showing how comparison of the performance of different technologies or evaluation of the effect of parasitic elements can be easily done. The tool is applied to the design of a power amplifier and a VCO at 910 MHz in 0.35 mum CMOS technology. The tools estimations are checked against simulations using BSIM3v3, showing very good agreement. Additionally, preliminary experimental results are presented

Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

A tool for design exploration and power optimization of CMOS RF circuits blocks

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

Low-cost signature test of RF blocks based on envelope response analysis

This paper demonstrated from the theory and measurements, that series-parallel (SP) mirrors allow building current copiers with copy factors of thousands, without degrading mismatch or noise performance. SP current-division is then employed to design OTAs ranging from a few pS to a few nS, with up to 1V linear range, consuming in the order of 100nW, and with a reduced area. An integrated 3.3s time-constant integrator was also presented. One-by-one several design non-idealities are revised: linearity, offset, noise, leakages; as well as layout techniques. A final analysis concludes that SP-association of transistors allows to build very efficient transconductors, for demanding applications in the field of implantable electronics among others