Eduardo J. Peralías

Practical oscillation-based test of integrated filters

Oscillation-based test (OBT) techniques show promise in detecting faults in mixed-signal circuits and require little modification. to the circuit under test. Comparing both the oscillations amplitude and frequency yields acceptable test quality. OBT seems especially appealing for filters but requires adaptation to handle monolithic circuits or the analog-core-based design of complex mixed-signal ICs.

Testing mixed-signal cores: a practical oscillation-based test in an analog macrocell

A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is to offer designers testing options that do not have significant area overhead, performance degradation, or test time. This work shows that OBT is a potential candidate for IP providers to use in combination with functional test techniques. We have shown how to modify the basic concept of OBT to come up with a practical method. Using our approach, designers can use OBT to pave the way for future developments in SoC testing, and it is simple to extend this idea to BIST.

Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs

Using several analog-to-digital converters (ADCs) in parallel with convenient time offsets is considered an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic description of the problem, studying the impact of time skews, gain, and offset mismatches. The probability density function of both signal-to-noise ratio (SNR) and spurious-free-dynamic range (SFDR) are explicitly calculated, giving access to important statistical parameters. It is shown that the SNR and SFDR dispersion should not be neglected in making practical considerations for design decisions.

A high-Q bandpass fully differential SC filter with enhanced testability

This work describes a 6th order high-Q Bandpass SC filter which has been designed to prove the feasibility of a unified on- and off-line testing approach. Several design issues to reduce the impact of extra circuitry in the performace, area and power dissipation overhead are discussed, and experimental results from a prototype are presented.

On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.

Structural testing of pipelined analog to digital converters

This paper presents two alternative BIST schemes for structural testing of pipelined ADCs. The operational principle of both strategies relies on testing each of the ADC stages reconfigured as an A/D-D/A block and applying as input a set of analog values. These values are DC stimuli giving a simple output signature. The new techniques are intended for being used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.

MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs

In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.

SWITTEST: automatic switch-level fault simulation and test evaluation of switched-capacitor systems

A tool for the switch-level fault simulation and test evaluationof switched-capacitor systems is presented. Time or frequency-domainfault simulations with SWITCAP and time-domain faultsimulations with HSPICE can be performed. Adequate fault modelsare presented for both simulators. The tool has proven to bevery useful in the early evaluation of test strategies, providing similarresults to those obtained at the transistor-level.

A DFT technique for analog-to-digital converters with digital correction

Pipeline or sub-ranging architectures enable the implementation of high-speed, low-power and high-resolution Analog-to-Digital Converters (ADCs). It is usual in these architectures to include digital correction to reduce the sensitivity to certain component nonlinearities, such as comparator offsets and settling errors. However, digital correction makes difficult the detection of defective operation because some errors could not be revealed in the output code under nominal test conditions but could appear when operation conditions change. This paper presents a Design-for-Testability (DFT) technique for concurrent error detection in digitally-corrected pipelined ADCs. The approach is based on hardware redundancy, requiring an additional sub-DAC, a window comparator and some control logic. The effectiveness of the technique has been evaluated by means of fault simulations in a switched-capacitor 10-bit ADC application example.

Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus

An adaptive digital test procedure for the static characterization of analog-to-digital converters (ADCs) is described in this paper. The proposed technique performs a blind and accurate estimation of the integral nonlinearity (INL) of the ADC under test (ADCUT) without requiring any particular test stimulus. Its practical implementation implies no modifications on the ADCUT analog section and needs a very simple low-cost digital logic, which makes this useful for: 1) simple digital automatic test equipment (ATE)-based ADC static test and 2) built-in self-test (BIST) for ADCs test working either in concurrent (online) or nonconcurrent (offline) modes. The validation of these test methods has been performed through realistic behavioral simulations including noise, mismatch, and nonlinear errors. Experimental results for a custom-designed pipeline ADC and for the commercial AD664 chip are also reported.