Raffaele De Rose

Comparative analysis of yield optimized pulsed flip-flops

Abstract In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte Carlo simulation results demonstrate that using transistor reordering and dual threshold voltage transistors timing, energy and energy-delay-product yields of more than 1.98, 1.62 and 1.99 times higher are obtained, without requiring architectural modifications and without increasing silicon area requirement. Several flip-flops optimized as described here are compared taking into account the effects due to random process variations and to environmental variations (caused by power supply voltage and temperature fluctuations). Obtained results show that among the compared circuits the Conditional Precharge Flip-Flop achieves the highest delay, energy and energy-delay-product yields.

Numerical Simulation on the Influence of Via and Rear Emitters in MWT Solar Cells

In this paper, we analyze, by means of numerical simulations, metal wrap through (MWT) silicon solar cells without a rear emitter and/or via an emitter that feature a Schottky contact between the Ag metal and the p-base. We show how the effective Schottky barrier height affects both dark and illuminated properties of the cell. An equivalent electrical model for the dark analysis is proposed, which accounts for the shunting effects and the thermionic-emission current at Ag/p-base contact. We investigate the figures of merit of MWT solar cells for different via configurations, highlighting the influence of the Ag/p-base barrier height. Moreover, the influence of the rear busbar width, as well as of the operating temperature, is analyzed.

Numerical Simulation and Modeling of Resistive and Recombination Losses in MWT Solar Cells

This study analyzes the impact of resistive and recombination losses in metal wrap through (MWT) solar cells through technology computer aided design (TCAD) numerical simulations. Two types of MWT architectures are considered in this study: “point busbar,” featuring one circular tabbing contact for each via at the back side, and “continuous busbar,” in which the rear busbar connects all the vias along a line. A comparison with conventional, H-pattern, front contact (FC) solar cells is performed by adopting the surface recombination velocity at the rear-contact isolation region as a parameter representative of possible passivation options. The differences under dark and light conditions are highlighted. Moreover, the following resistive losses in MWT cells are investigated: via resistance, shunting effect, and lateral conduction of charge carriers above rear busbar. An analytical model to account for the lateral conduction of charge carriers is proposed and validated by means of numerical simulations. While the advantage of MWT over FC cells is confirmed by simulation, we quantitatively show how the resistive and recombination losses limit the efficiency of MWT cells.

An Ultralow-Voltage Energy-Efficient Level Shifter

This brief presents an energy-efficient level shifter (LS) able to convert extremely low level input voltages to the nominal voltage domain. To obtain low static power consumption, the proposed architecture is based on the single-stage differential-cascode-voltage-switch scheme. Moreover, it exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption, while a split input inverting buffer is used as the output stage to further improve energy efficiency. When implemented in a commercial 180-nm CMOS process, the proposed design can up-convert from the deep subthreshold regime (sub-100 mV) to the nominal supply voltage (1.8 V). For the target voltage level conversion from 0.4 to 1.8 V, our LS exhibits an average propagation delay of 31.7 ns, an average static power of less than 60 pW, and an energy per transition of 173 fJ, as experimentally measured across the test chips.

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics

In this paper, the influence of random process variations on speed and energy consumption of various classes of flip-flops is analyzed. Differently from previous works, the process variability impact has been evaluated on physical designs. Moreover, the combined effects of process and environmental variations were also analyzed to recognize more robust flip-flop topologies.

Impact of process variations on pulsed flip-flops: yield improving circuit-level techniques and comparative analysis

Process variations cause unpredictability in speed and power characteristics of nanometer CMOS circuits impacting the timing and energy yields. In this paper, transistor reordering and dual-Vth techniques are evaluated regarding their efficiency in mitigating the impact of process variations on a set of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 1.62X and 1.99X times, respectively. The yield optimized flip-flop circuits are also comparatively analyzed to identify the best topologies.

A variation-aware simulation framework for hybrid CMOS/spintronic circuits

In this paper, a variation-aware simulation framework is introduced for hybrid circuits comprising MOS transistors and spintronic devices (e.g., magnetic tunnel junction-MTJ). The simulation framework is based on one-time characterization via micromagnetic multi-domain simulations, as opposed to most of existing frameworks based on single-domain analysis. As further distinctive capability, stochastic variations of the MTJ switching are explicitly incorporated through a Skew Normal distribution, which is adjusted to fit micromagnetic simulations. The framework is implemented in the form of Verilog-A look-up table based model, which assures easy integration with commercial circuit design tools, and very low computational effort. The framework is applied to non-volatile Flip-FIops as case study with 10,000 Monte Carlo runs.

Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework

In this paper, we focus on the study of the impact of voltage scaling on writing performance and energy of STT-MRAM arrays featuring four different configurations of bitcell. The memory arrays are implemented by a circular MTJ with a diameter of 30 nm and a 28-nm UTBB FDSOI CMOS technology. The analysis is performed by considering the effect of both CMOS and MTJ process variations, and the stochastic variations of the MTJ switching time. The MTJ behavior is integrated into a commercial circuit design tool in the form of a Verilog-A LUT-based code, which exploits as inputs the outcomes of micromagnetic multi-domain simulations to ensure more accurate modeling of the MTJ characteristics. Simulation results show that the write performance and energy of STT-MRAMs strongly depend on the bitcell configuration. The energy saving achieved through voltage scaling is found to be up to 37% at the cost of a delay penalty of 3.3×, as compared to the write operation at the nominal voltage of 1 V.

A physical unclonable function based on a 2-transistor subthreshold voltage divider

Summary In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUFs) is presented. The proposed solution exploits the variability of a simple voltage divider, implemented by two identical series-connected nMOSFETs in a commercial 65-nm CMOS process, to generate a random and stable nanokey. Both the transistors are biased in the subthreshold regime to enhance the output voltage dispersion and consequently the variability of the PUF response. The bit key generation is obtained by comparing the analog outputs of a pair of voltage dividers. Monte Carlo simulations on 10,000 samples have been performed to deduce the design guidelines for transistor sizing aimed at ensuring a high robustness of the PUF response against noise, supply voltage, and temperature variations. When compared with some state-of-the-art PUF designs, the proposed circuit solution proves to be a promising and competitive candidate for implementing analog and static PUFs featuring small area occupancy, low-power features, and high reliability. Copyright

Design and evaluation of high-speed energy-aware carry skip adders

In this paper, the impact of different dynamic logic design styles is evaluated considering as benchmark a fast carry-skip adder. Four different adder designs were implemented in standard domino, footless domino, data driven dynamic, and dynamic hybrid (standard domino + data driven dynamic) logic design styles, by exploiting the STMicroelectronics 45nm 1V CMOS technology. When applied to a 32-bit carry-skip adder, the data driven dynamic approach assures an energy-delay product 29%, 33% and 39% lower than the standard domino, footless domino, and dynamic hybrid implementations, respectively.