P. Markondeya Raj

Polymer-ceramic nanocomposite capacitors for system-on-package (SOP) applications

This work focuses on optimizing the dispersion of nanosized ceramic particles for achieving higher dielectric constant, thereby higher capacitance density in polymer/ceramic nanocomposites. It has been observed that high solids loading leads to entrapment of porosity in the microstructure which lowers the effective dielectric constant of the films. The amount of solvent in the suspension and the speed at which spin coating was performed were found to impact the dielectric constant of high filler content nanocomposites. The interplay between the rheological properties of the suspension and processing parameters such as solvent content and coating speeds and its impact on the dielectric properties of the film are discussed. Porosity of thin film composites was measured for the first time to study the impact of these processing parameters. Powders of different particle sizes were mixed to obtain bimodal particle size distribution in order to increase the packing density of the composite. Packing density was improved by modifying the dispersion methodology. A nanocomposite with dielectric constant as high as 135 was obtained for the first time in the low-cost printed wiring board compatible epoxy system. A capacitance densities of /spl sim/35 nF/cm/sup 2/ on a nominal 3.5 micrometer films was achieved on PWB substrates with high yield. The manufacturability of these formulated nanocomposites and their applications as decoupling capacitors have been tested using a large area (300 mm /spl times/ 300 mm) system-on-package (SOP) chip-to-chip communication test vehicle.

Trend from ICs to 3D ICs to 3D systems

Moores Law has driven the IC industry to a billion transistor chip. But major technical and financial barriers are foreseen beyond 32 nm. One alternative path to this challenge seems to be stacked 3D ICs. But 3D ICs are a small part of any system and the total benefits of miniaturization cannot be realized until the entire system is miniaturized. This is the basis of 3D systems, the focus of this paper. The 3D miniaturization technologies briefly described in this paper include Si or wafer level interposers with Through-Package-Vias (TPV), nano-scale passives, thermal materials and interfaces and fine pitch system interconnections.

Highly-reliable, 30µm pitch copper interconnects using nano-ACF/NCF

Flip chip packaging of ultra fine pitch integrated circuits (ICs) on organic substrates aggravates the stress-strain concerns, requiring a fundamentally different system approach to interconnections, underfill, interfaces, and the substrate. This work demonstrates a novel interconnection solution with excellent reliability for ultra-fine pitch (∼30µm) silicon (Si) on organic first level interconnections by using copper (Cu) pillar with nano-anisotropic conductive film (nano-ACF)/non conductive Film (NCF).

Antenna miniaturization using magneto-dielectric substrates

Effective antenna miniaturization is a challenging problem due to the inevitable trade-off between the size and the performance of the antenna due to the fact that antenna performance is bound with the fundamental limits based on the size of the antenna. Antenna miniaturization is also a critical issue since the key component determining the size of a mobile device is usually the antenna. Recent studies on novel materials called magneto-dielectrics have raised hope to miniaturize the antenna effectively. Magneto-dielectrics are materials with both the relative permittivity (∊r) and the relative permeability (µr) of the substrate greater than unity. In this paper, several issues regarding the magneto-dielectrics and their application to the antenna miniaturization are investigated. The theoretical reason why the magneto-dielectrics are better substrates for planar antennas than the dielectric materials is investigated along with a material synthesis technique to explain how to realize these materials. Additionally, a characterization methodology to extract the frequency dependent properties (∊′, ∊″ µ′, and µ″) of these materials is presented in this paper. Finally, the advantages and the limitations of these substrates for antenna applications are discussed in the paper.

Mid frequency decoupling using embedded decoupling capacitors

Surface mount technology (SMT) decoupling capacitors fail to provide decoupling above 100MHz. This paper presents the use of embedded thin film capacitors to provide decoupling in the mid frequency range from 100MHz to 2GHz. On-chip capacitance provides decoupling above 2GHz. The effect of chip, package and board capacitors on the performance of digital systems is analyzed taking into account the parasitic effects of power/ground planes, vias and solder balls. A synthesis and selection methodology for embedded package capacitors is also presented.

Copper interconnections for high performance and fine pitch flip chip digital applications and ultra-miniaturized RF module applications

Copper is an excellent candidate material for next generation of chip-package interconnections because of its high electrical and thermal conductivities, good mechanical properties at assembly and operating temperatures and well-established infrastructure to integrate with back-end processes with electroplating technology downscalable to nanoscale. This technology can also accommodate the increasing I/O density of future microprocessors with the best electrical and mechanical performance. In addition, embedment of active components with chip-last approach being proposed by Georgia Tech PRC can also be realized with the shortest interconnections resulting in performance and miniaturization comparable to chip-first approach. There is an increasing trend to replace solders with copper because of these advantages. In this paper, we describe the current status of copper bumping and copper interconnection and assembly technologies and show our future strategy

Low temperature, low profile, ultra-fine pitch copper-to-copper chip-last embedded-active interconnection technology

In a continuous drive to achieve low form-factor packages, chip-to-package interconnections have evolved from the conventional solders to a more hybrid technology consisting of copper and solder. However, scaling down the bump pitch to increase the interconnect density poses serious reliability and yield issues. In the previous, a low-profile interconnect architecture, ~20µm total height, was demonstrated comprising of copper-to-copper interconnection and novel adhesive materials. This paper focuses on: (1) design and fabrication of test vehicles to assess the robustness of the interconnect architecture, (2) assembly process development for copper-to-copper interconnections, and (3) reliability and failure analysis of the interconnection. Excellent reliability results are demonstrated under thermal cycling test (TCT) using non-conductive films (NCF) as adhesive. This interconnect scheme is also shown to perform well with different die sizes, die thicknesses and with embedded dies thus offering a great potential for integration with flip chip packages as well as with chip-last embedded active chips in organic substrates. A simple and reliable low-cost and low-temperature direct Cu-Cu bonding is thus demonstrated for the first time.

Magnetic nanocomposites for organic compatible miniaturized antennas and inductors

Current wireless systems are limited by RF technologies in their size, communication range, efficiency and cost. RF circuits are difficult to miniaturize without compromising performance. Antennas and inductors are major impediments for system miniaturization because of the lack of magnetic materials with suitable high frequency properties. Keeping antenna and inductor requirements into consideration, two magnetic nanocomposite systems - silica coated cobalt-BCB and Ni ferrite-epoxy were investigated as candidate materials. Nanocomposite thick film structures (125-225 microns) were screen printed onto organic substrates. Parallel plate capacitors and single coil coplanar inductors were fabricated on these films to characterize the electrical and magnetic properties of these materials at low and high frequencies. Electrical characterization showed that the Co/SiO/sub 2/ nanocomposite sample has a permeability and a matching permittivity of /spl sim/10 at GHz frequency range making it a good antenna candidate. Both polymer matrix composites retain high permeability at 1-2 GHz.

Selection and evaluation of materials for future system-on-package (SOP) substrate

This work deals with the selection and evaluation of candidate materials as a future base substrate for SOP. New composite materials using advanced fiber clothes and fillers were fabricated and tested to evaluate the increase in performance compared to conventional glass-epoxy substrates (FR-4). Composites built with advanced carbon-cloth having a negative thermal expansion coefficient (CTE) yielded a composite CTE of <3 ppm//spl deg/C. The composites have 2-3 times higher modulus than conventional FR-4. In order to evaluate materials with further higher modulus, metal matrix composites Al/SiC with low CTE of 7 ppm//spl deg/C and high modulus of 220 GPa were also considered. The thermomechanical reliability of the electrical interconnections was evaluated after assembling flip-chips on three different substrates by subjecting test vehicles to thermal shock treatments. The failure modes in different substrates were analyzed with optical microscopy. The stresses in the solder joints and dielectric layer were also estimated with analytical and finite element models (FEM).

Large silicon, glass and low CTE organic interposers to printed wiring board SMT interconnections using copper microwire arrays

This paper reports SMT-compatible stress-relief microwire arrays in thin polymer carriers, as a unique, novel and low-cost solution for reliable board-level interconnections between large silicon, glass and low coefficient of thermal expansion (CTE) organic interposers and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled onto the back of the interposer as a stress-relief interlayer. Such a structure is assembled onto the board using standard SMT processes. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (300-400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. The first part of the paper describes the design of microwire array to meet the thermo-mechanical reliability requirements. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. Strip models were built to study the reliability of 400 μm-pitch interconnections with a 100 μm thick, 20 mm × 20 mm silicon interposer that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared with that of ball grid array (BGA) interconnection, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of the microwire array. Flexible thermoplastic polyimide films were used as the polymer film carriers for the microwire interconnection structure. In the initial feasibility demonstration, 100 μm thick films with laminated copper foil on both sides of the dielectric were used. A 308 nm excimer laser source was used to ablate the via arrays in the polymer. The microwires were batch fabricated by bottom-up electrolytic plating through the polymer template. A low-cost approach to the microwire fabrication is thus demonstrated by partially releasing the wires with controlled etching of the polymer carrier.