Rainer Thoma

Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers

We report an interdigitated p-i-n photodetector fabricated on a 1-/spl mu/m-thick Ge epitaxial layer grown on a Si substrate using a 10-/spl mu/m-thick graded SiGe buffer layer. A growth rate of 45 /spl Aring//s/spl sim/60 /spl Aring//s was achieved using low-energy plasma enhanced chemical vapor deposition. The Ge epitaxial layer had a threading dislocation density of 10/sup 5/ cm/sup -2/ and a rms surface roughness of 3.28 nm. The 3-dB bandwidth and the external quantum efficiency were measured on a photodetector having 1-/spl mu/m finger width and 2-/spl mu/m spacing with a 25/spl times/28 /spl mu/m/sup 2/ active area. At a wavelength of 1.3 /spl mu/m, the bandwidth was 2.2, 3.5, and 3.8 GHz at bias voltages of -1, -3, and -5 V, respectively. The dark current was 3.2 and 5.0 /spl mu/A at -3 and -5 V, respectively. This photodetector exhibited an external quantum efficiency of 49% at a wavelength of 1.3 /spl mu/m.

A Physically-Based Compact Model for LDMOS Transistors

This paper presents a physically based model for LDMOS transistors. The model advances the state-of-the-art by using a formulation applicable across a wide voltage range, by accounting for the distributed parasitic metal effects, and by properly modeling the bias dependence of parasitic capacitances. The model is implemented in Motorola’s internal simulator MCSPICE.

Fabrication and modeling of gigahertz photodetectors in heteroepitaxial Ge-on-Si using a graded buffer layer deposited by low energy plasma enhanced CVD

Photodetectors were fabricated in a heteroepitaxial Ge-on-Si deposited by low energy plasma enhanced CVD. Dark current density of 4.6 nA//spl mu/m, 49 % quantum efficiency, and a -3 dB bandwidth of 3.5 GHz were measured at 1.3 /spl mu/m wavelength and -3 V bias. Numerical simulations predict device modifications can achieve 10 Gbps (/spl cong/ 7 GHz) bandwidth.

Simulation and verification of the hot carrier degradation behavior in an analog high-voltage device with graded channel profile

We compare the behavior of standard and high-voltage graded channel MOSFETs in a 0.35 μm BiCMOS technology platform under high-voltage stress conditions. This work is focused on explaining the extreme robustness of the high-voltage device against degradation from hot carrier injection with the help of TCAD simulations. Hot carrier injection does not occur in the channel region, but in the drain finger extension under the gate oxide. The device parameter shift with accumulated gate charge is small compared to standard devices.

Signal integrity implications of inductor-to-circuit proximity

Signal integrity is one of the major challenges in system-on-a-chip (SOC) integration. The complexity of the associated problems increases when RF circuits are integrated together with other circuits, such as digital or large signal circuits. In this material, an analysis of possible interactions between an on-chip inductor and various types of circuit blocks is described. Conclusions on the feasibility of an inductor-circuit system are outlined.

A three-dimensional, physically based compact model for IC VDMOS transistors

Abstract A three-dimensional VDMOS model has been derived and implemented in SPICE. The model was developed and characterized for the square cell, rectangular grid device layout for Motorolas SmarTMOS ™ technologies. The model includes physical models for R DSon over gate voltage, temperature and cell number. It also includes accurate, scalable models for the gate-charge, including the voltage-varying gate-drain capacitance and the distributed effects of the buried layer and interconnect metal resistances on the total on-resistance of the device. This allows efficient and accurate modeling of typical VDMOS layouts.