Raj Pulugurtha

Magneto-Dielectric Nanocomposite for Antenna Miniaturization and SAR Reduction

A 900-MHz meander planar inverted-F antenna (PIFA) on a magneto-dielectric nanocomposite (MDNC) substrate for mobile communication is presented. Cobalt nanoparticles were synthesized with polymer matrix, and its properties were measured up to 4 GHz. Bandwidth, gain, and radiation efficiency of antenna on different substrates (MDNC, High K material, and FR4) were compared, and it is demonstrated that MDNC is beneficial for antenna miniaturization with acceptable antenna performance. Head effects due to the antenna were studied, and specific absorption rate (SAR) was calculated. The simulation results demonstrate that the MDNC reduces the head effects and the magnetic loss of MDNC helps to decrease SAR due to the antenna.

Low cost, high performance, and high reliability 2.5D silicon interposer

This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. The polycrystalline Si interposer with 100-200μm thick raw Si, obtained without any back-grind or polish, and double side processing, without the use of carriers, has the potential to reduce the cost of wafer-based Si interposers by 2× and up to 10× by scaling to large panels. Thick polymer liner reduces the electrical loss of TPVs dramatically, by an order of magnitude compared to TSVs with SiO2 liner. Initial reliability of TPVs at 150μm and 200μm pitch was demonstrated with daisy chains passing 1000 thermal cycles from -55°C to 125°C. The paper concludes with Cu-SnAg microbump assembly at 50μm pitch onto panel Si interposers with Cu-polymer RDL routing at 4-5μm line lithography.

RF Characterization of Magnetodielectric Material Using Cavity Perturbation Technique

Magnetodielectric (MD) materials find application in many areas of microwave engineering, and therefore, measurement of their dielectric and magnetic properties is very important. This paper presents a novel MD material characterization method using the cavity perturbation technique (CPT) with substrate-integrated waveguide (SIW) cavity resonators. Frequency dependent complex permittivity and permeability of MD material can be extracted with a single SIW cavity structure by inserting the sample material into different locations. The fundamental theory of CPT is explained and its analysis for SIW cavity is discussed. Cobalt nanoparticles are synthesized with a fluoropolymer matrix to realize the MD materials and their properties are measured in the frequency range 1-4 GHz. The effect of volume fraction and density of the synthesized MD materials on the dielectric and magnetic properties has been studied.

System-on-a-package (SOP) substrate and module with digital, RF and optical integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, and optical system integration on a single package. SOP aims to utilize the best of on-chip SOC integration and package integration to achieve the highest system performance at the lowest cost. The micro-miniaturized multi-functional SOP package is highly integrated and fabricated on large area substrates similar to the wafer-to-IC concept. In addition to novel mixed signal design methodologies, SOP research at PRC is targeted at developing enabling technologies for package level integration including ultra-high density wiring, embedded passive components, embedded optical interconnects, wafer level packaging and fine pitch assembly. Several of these enabling technologies have been recently integrated into the first successful system level demonstration of SOP technology using the intelligent network communicator (INC) testbed. This paper reports on the latest INC and SOP testbed results at the PRC and provides an insight into the future SOP integration strategy for convergent microsystems. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation.

Analysis on the miniaturization of reactive impedance surfaces with magneto-dielectrics

Miniaturization of the reactive impedance surfaces with the magneto-dielectric substrates is studied in this paper with their comparison to the high permittivity substrates. It has been found that magneto-dielectrics can provide wider reflection phase bandwidth while providing the same miniaturization with the high permittivity substrates. The application of these miniaturized surfaces to the low-profile microstrip patch antenna designs has also been included in this paper. It has been shown that the reactive impedance surfaces miniaturized with the magneto-dielectric materials provide better improvement in the bandwidth of the antenna compared to the reactive impedance surfaces miniaturized with the high permittivity substrates. It has also been found that the gain and the front-to-back ratio of the antennas on both type of substrates can be improved with the inclusion of RIS. Moreover, it has been observed that RIS performance becomes similar to that of a PEC ground plane as the size of the RIS decreases.

Demonstration of Enhanced System-Level Reliability of Ultra-Thin BGA Packages with Circumferential Polymer Collars and Doped Solder Alloys

The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100μm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and 100-200μm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dip-flux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250μm BGA at 400μm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moiré warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition.

Analysis of System-Level Reliability of Single-Chip Glass BGA Packages with Advanced Solders and Polymer Collars

Emerging high-performance computing systems have been aggressively driving advances in packaging technologies to meet their escalating performance and miniaturization needs. Large, high-density 2.5D silicon interposers have gained momentum with the recent split-die trend but face critical reliability challenges at board-level that are addressed by introducing an additional organic BGA package between interposer and board. Glass substrates have emerged as a promising alternative owing to the superior electrical properties, sub-5µm lithographic capability and tunable CTE of glass that enables direct SMT assembly to mother boards among other advantages. This paper investigates board-level reliability of single-chip glass BGA packages, 18.5mm × 18.5mm in body size and 100µm in thickness at 400µm BGA pitch. A parametric finite-element analysis was performed to extract the optimum glass CTE for balanced chip-and board-level reliabilities. Innovative doped solder materials and strain-relief mechanisms were evaluated to improve board-level reliability with minimum system-level impact. Daisy-chain test vehicles with low (3.3ppm/K) and high (9.8ppm/K) CTE glass substrates were fabricated and assembled at chip and board levels by Cu pillar thermocompression bonding and standard SMT reflow, respectively. Assemblies with different BGA solder alloys, SAC105, SAC305 and Indiums Mn-doped SACmTM, were subjected to thermal cycling test according to JEDEC standards. Comprehensive failure analysis was performed to evaluate fatigue life improvements with advanced interconnection materials and conclude on scalability of glass substrates for high-performance applications.

Machine-Learning Approach for Design of Nanomagnetic-Based Antennas

We propose a machine-learning approach for design of planar inverted-F antennas with a magneto-dielectric nanocomposite substrate. It is shown that machine-learning techniques can be efficiently used to characterize nanomagnetic-based antennas by accurately mapping the particle radius and volume fraction of the nanomagnetic material to antenna parameters such as gain, bandwidth, radiation efficiency, and resonant frequency. A modified mixing rule model is also presented. In addition, the inverse problem is addressed through machine learning as well, where given the antenna parameters, the corresponding design space of possible material parameters is identified.

Thermocompression Bonding Process Design and Optimization for Warpage Mitigation of Ultra-Thin Low-CTE Package Assemblies

Increasing needs for functionality, performance and system miniaturization in fine-pitch consumer applications have been driving a new class of ultra-thin interposers and packages with larger body sizes, aggravating warpage. These trends gave rise to serious concerns for assembly yield and reliability, especially at board level. The recent adoption of substrate technologies with silicon-matching coefficient of thermal expansion (CTE) reinforces these concerns by introducing a large CTE mismatch between package and organic board. Warpage control and mitigation in assembly has, therefore, become critical in enabling reliable SMT interconnection of ultra-thin, large, low-CTE BGA packages to the board. Copper pillar thermocompression bonding (TCB) has emerged as a key assembly technology to improve die assembly yield at pitches below 80μm and large die sizes. In TCB, heat is applied from the die side only while the substrate is maintained at a low stage temperature, as opposed to isothermal heating in mass reflow. The temperature gradient in the package can, therefore, be finely tuned providing control over the warpage behavior. This paper investigates TCB-induced warpage and its dependence on the bonding thermal profiles in a single-chip, 200μm-thick, low-CTE organic package at 50μm pitch and 17mm x 17mm body size. Warpage trends as a function of the stage temperature were first predicted with a simple coupled thermal-structural finite-element model, then experimentally validated by Shadow-Moiré measurements of assemblies built with varying stage temperatures from 70°C to 150°C. Interactions with the thermocompression tool, in particular the effect of vacuum-coupling of the substrate to the stage, were considered and investigated. Guidelines for design of TCB profiles for warpage minimization were finally derived with considerations of assembly throughput to improve board-level SMT yield and system-level reliability.