I.R. Abothu

New paradigm in IC package interconnections by reworkable nano-interconnects

We propose new IC packaging technologies that have the potential to bring about disruptive innovations in interconnect pitch, best electrical and mechanical properties, low-cost and chip size. Current approaches for chip to package interconnections are limited in terms of either pitch or electrical-mechanical trade-off properties. For example, lead free solder interconnects fail mechanically as the pitch is brought down from current 200 micron pitch to 20 micron. Compliant leads, on the other hand, solve mechanical reliability but at the expense of electrical performance. Solution-derived materials for reworkable nano-interconnects can be a viable technology to meet these two challenges. Nano-grained electroplated copper is chosen as the primary interconnect material. Compliancy was addressed by tuning the process to electroplate high-aspect-ratio structures. Reworkability was addressed by a thin, liquid lead-free solder interface between the interconnect and the package. Two approaches, sol-gel and electroless plating were used in this work to deposit these liquid interface films of lead free solders of the order of 50-300 nm. In the sol-gel process, metal-organic polymer solutions were heat-treated in a reducing atmosphere at 300/spl deg/C to form lead-free solders (Sn-Ag-Cu). In the other approach, lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents. This process was done at temperatures of 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation. Lead-free solder films formed from both the above approaches were demonstrated to bond copper pads. Solution-derived nano-solder technology is an attractive low-cost method for bump-less nano-interconnects and other applications such as MEMS hermetic packaging and compliant interconnect bonding.

Magnetic nanocomposites for organic compatible miniaturized antennas and inductors

Current wireless systems are limited by RF technologies in their size, communication range, efficiency and cost. RF circuits are difficult to miniaturize without compromising performance. Antennas and inductors are major impediments for system miniaturization because of the lack of magnetic materials with suitable high frequency properties. Keeping antenna and inductor requirements into consideration, two magnetic nanocomposite systems - silica coated cobalt-BCB and Ni ferrite-epoxy were investigated as candidate materials. Nanocomposite thick film structures (125-225 microns) were screen printed onto organic substrates. Parallel plate capacitors and single coil coplanar inductors were fabricated on these films to characterize the electrical and magnetic properties of these materials at low and high frequencies. Electrical characterization showed that the Co/SiO/sub 2/ nanocomposite sample has a permeability and a matching permittivity of /spl sim/10 at GHz frequency range making it a good antenna candidate. Both polymer matrix composites retain high permeability at 1-2 GHz.

Embedded decoupling capacitor performance in high speed circuits

Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of a high speed digital board/package because of its shorter leads that result in smaller parasitic inductance. This leads to lower impedance over a higher frequency band. It is presumably better in reliability and lowers the cost as well. Designers tend to use large value capacitors for efficient decoupling. Usually, to increase capacitance of an embedded capacitor, one can use a material with higher dielectric constant, design larger electrodes, and reduce the thickness of the dielectric. However, these strategies may sometimes lead to lower performance at high frequency band. This paper will discuss the pros and cons of different embedded capacitor approaches through simulation. As an application example, a typical power/ground network with an embedded capacitor will be compared with that of surface mount discrete capacitor.

Development of high-k embedded capacitors on printed wiring board using sol-gel and foil-transfer processes

Sol-gel ceramic films were fabricated for organic system-on-package compatible integral capacitor applications. The films were synthesized on Ti and Ni foils which were then transferred onto organic boards using a lamination step. SrTiO/sub 3/ and BaTiO/sub 3/ films were synthesized with capacitance as high as 700 nF/cm/sup 2/ and loss as low as 0.005. It should be noted that the high permeability of Ni (approximately 100 in bulk form) and lower conductivity compared to copper decreases the skin depth and increases the resistivity of copper. This can have a deleterious effect on Q. More studies are underway to investigate this effect.

Integrating High-k Ceramic Thin Film Capacitors into Organic Substrates Via Low-Cost Solution Processing

Current organic package-compatible embedded decoupling capacitors are based on thick film (8-16 m) polymer-ceramic composites with dielectric constant (k) of 20-30 and do not have sufficient capacitance density to meet the impedance requirements for emerging high-speed circuits and high power density microprocessors. High-k/high capacitance density ceramics films that can meet the performance targets are generally deposited by high-temperature processing or costly vacuum technology (radio frequency sputtering, PECVD) which are expensive and also incompatible with organic packages. The objective of this project is to develop ultra thin films (100-300nm) with high dielectric constant using organic compatible processes to meet future decoupling applications. In the current study, direct deposition of crystalline ceramic films on organic boards at temperatures less than 100C was demonstrated with the hydrothermal method. Post-hydrothermal treatments were shown to minimize the defects in the as-synthesized hydrothermal barium titanate films and improve the breakdown voltage (BDV) and leakage characteristics. Thin films with high capacitance densities and breakdown voltages of 10V were demonstrated. As an alternate technique, sol-gel technology was also demonstrated to integrate ceramic thin films in organic packages. A major barrier to synthesis of sol-gel films on copper foils is the process incompatibility of the sol-gel barium titanate with the copper electrodes. To enable process compatibility, process variables like sol pyrolysis temperature and time, and sintering conditions/atmosphere were optimized. Capacitance densities above 1.1F/cm was demonstrated on commercial copper foils with a BDV above 10 V. The two technologies reported in this study can potentially meet midfrequency decoupling requirements of digital systems.

Simultaneous switching noise suppression using hydrothermal barium titanate thin film capacitors

This paper reports the integration of hydrothermal barium titanate thin film embedded capacitors in organic printed wiring boards. These capacitors have 300 nm thick dielectrics with k>350, can attain capacitances of 1 /spl mu/F/cm/sup 2/ and are ideal for decoupling applications. In order to evaluate these films for simultaneous switching noise suppression, a clock distribution network was designed using a clock driver with one input and four differential outputs. The design consists of a clock driver and four pairs of impedance controlled transmission lines with embedded decoupling capacitors. In order to evaluate the effects of capacitance value and the type of capacitor /sub i/screte vs. embedded, coupons with different embedded capacitance values and discrete capacitors were fabricated on the same board. The fabricated structures were simulated using the transmission matrix method (TMM) in the frequency domain and a macromodeling method in the time domain. This paper demonstrates for the first time that the simple low-cost, aqueous based low-temperature film growth technique can provide the best solution for embedded decoupling capacitor problems in organic packages.

System-on-a-package (SOP) substrate and module with digital, RF and optical integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, and optical system integration on a single package. SOP aims to utilize the best of on-chip SOC integration and package integration to achieve the highest system performance at the lowest cost. The micro-miniaturized multi-functional SOP package is highly integrated and fabricated on large area substrates similar to the wafer-to-IC concept. In addition to novel mixed signal design methodologies, SOP research at PRC is targeted at developing enabling technologies for package level integration including ultra-high density wiring, embedded passive components, embedded optical interconnects, wafer level packaging and fine pitch assembly. Several of these enabling technologies have been recently integrated into the first successful system level demonstration of SOP technology using the intelligent network communicator (INC) testbed. This paper reports on the latest INC and SOP testbed results at the PRC and provides an insight into the future SOP integration strategy for convergent microsystems. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation.

Recent advances in low CTE and high density system-on-a-package (SOP) substrate with thin film component integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, optical, and sensor functions integrated in a single package/module. The goal of this effort is to develop a platform substrate technology providing very high wiring density and embedded thin film passive and active components using PWB compatible materials and processes. The latest SOP baseline process test vehicle has been fabricated on novel Si-matched CTE, high modulus C-SiC composite core substrates using 10mum thick BCB dielectric films with loss tangent of 0.0008 and dielectric constant of 2.65. A semi-additive plating process has been developed for multilayer microvia build-up using BCB without the use of any vacuum deposition or polishing/CMP processes. PWB and package substrate compatible processes such as plasma surface treatment/desmear and electroless/electrolytic pulse reverse plating was used. The smallest line width and space demonstrated in this paper is 6mum with microvia diameters in the 15-30mum range. This build-up process has also been developed on medium CTE organic laminates including MCL-E-679F from Hitachi Chemical and PTFE laminates with Cu-Invar-Cu core. Embedded decoupling capacitors with capacitance density of >500nF/cm2 have been integrated into the build-up layers using sol-gel synthesized BaTiO3 thin films (200-300nm film thickness) deposited on copper foils and integrated using vacuum lamination and subtractive etch processes. Thin metal alloy resistor films have been integrated into the SOP substrate using two methods: (a) NiCrAlSi thin films (25ohms per square) deposited on copper foils (Gould Electronics) laminated on the build-up layers and two step etch process for resistor definition, and (b) electroless plated Ni-W-P thin films (70 ohms to few Kohms per square) on the BCB dielectric by plasma surface treatment and activation. The electrical design and build-up layer structure along with key materials and processes used in the fabrication of the SOP4 test vehicle were presented in this paper. Initial results from the high density wiring and embedded thin film components were also presented. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation

Integration and high-frequency characterization of PWB-compatible pure barium titanate films synthesized by modified hydrothermal techniques (< 100/spl deg/C)

This work reports synthesis of pure Barium Titanate films on Printed Wiring Board at temperatures less than 10v C using hydrothermal synthesis technique. The films thus synthesized were found be crystalline with gain size of 80100 nm. The film thickness was found to be 300 nm and the capacitance density was in the order of 1 pF/cm*, resulting in a dielectric constant of 400. Films grown on thiier Ti foils (42 microns) showed almost 100 % yield. High frequency dielectric properties were obtained from s-parameter measurements using a multi-line calibration approach and were found to be stable up to 8 GHz. Low-cost and low temperature synthesis and stable dielectric properties in the GHz frequencies make them ideal candidates for integral capacitor applications.

Processing, Properties and Electrical Reliability of Embedded Ultra-Thin Film Ceramic Capacitors in Organic Packages

Traditional ceramic thick films have served the need for decoupling applications but require too high a temperature processing to be embedded in organic packages. Copper foil compatible sol-gel-derived ferroelectric thin film integration addresses this problem due to its unique advantages such as the ability to precisely control the composition of the films, large-area manufacturability using simple and inexpensive equipment and ease of introducing dopants to engineer the dielectric properties like loss tangent and DC leakage characteristics. This paper presents synthesis, fabrication, electrical characterization and electrical reliability test of embedded ultra thin film (200-300nm) capacitors with capacitance density >2muF/cm2, low-loss, low leakage current and high breakdown voltage via sol-gel technology & foil lamination. Further, we investigated the effect of (i) smoothness of the foil and (ii) non-stochiometery on the microstructure as well as on the electrical properties of sol-gel barium titanate thin films on bare copper foil. The capacitance densities, leakage characteristics and electrical reliability data demonstrate the suitability of this technology for future embedded decoupling capacitor applications.