Rajan K. Pandey

Effect of Band-to-Band Tunneling on Junctionless Transistors

We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs). A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions. This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs. This BTBT leads to a nonnegligible increase in the off-state leakage current, which needs to be understood and alleviated. In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential. This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the off state. Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT. We present guidelines to optimize the device for high on-to-off current ratio. Finally, we compare the off-state leakage of bulk JLTs with that of silicon-on-insulator JLTs.

A Tunnel FET for

We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

V_{DD}

The efficient and successful realization of low-power semiconductor devices demands, among other things, the ability to quantitatively model and minimize myriad leakage phenomena. We report herein a general physical model to quantitatively compute crystallographic-orientation-dependent gate-induced drain leakage (GIDL), and its numerical implementation in a continuum-based device simulator. This simulation model has been successfully compared with relevant experimental data derived from heavily doped vertical diodes and 45-nm silicon-based CMOS devices. Also, the process optimization of next-generation 32-nm low-power devices has been discussed in the context of GIDL.

Scaling Below 0.6 V With a CMOS-Comparable Performance

DC and AC NBTI in deep EOT scaled HKMG p-MOSFETs with different IL (scaled to sub 2Å) are measured by UF-MSM method with 10μs delay. A model with interface trap generation (ΔV_IT-IL) at Si/IL interface, hole trapping (ΔV_HT) in IL bulk and trap generation (ΔV_IT-HK) linked to H passivated Oxygen vacancy (Ov-H) defects in IL/HK interfacial transition layer has been proposed. The existence of Ov defects and their energy levels are verified using DFT simulation. The model can successfully predict V_T shift (ΔV_T) during and after DC stress, dependence on pulse duty cycle (PDC) and frequency (f) for AC stress, and gate insulator process dependence with consistent set of parameters. Impact of EOT scaling on DC and AC NBTI is studied, and end-of-life degradation has been estimated.

Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs

The ability to understand and model the performance limits of nanowire transistors is the key to the design of next generation devices. Here, we report studies on high-mobility junctionless gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm(2)/V·s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.

A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs

Independent Trap Generation (TG) monitors such as DCIV and SILC have been used during NBTI, PBTI (and TDDB) stress in differently processed HKMG devices. TG from DCIV for NBTI is attributed to Si/IL and IL/HK interfaces; TG from DCIV for PBTI to IL/HK interface but at similar energy location as NBTI. TG from DCIV shows similar stress bias (VG,STR), time (tSTR) and temperature (T) dependence for NBTI and PBTI, while TG for PBTI from SILC shows very different dependence as it likely scans TG at different spatial and energetic locations. TG contribution to VT shift (ΔVT) is compared to ΔVT from ultra-fast measurements. A compact model is used to predict overall BTI ΔVT considering uncorrelated contributions from independently measured TG and trapping (TP) in pre-existing and generated bulk traps. Impact of IL scaling on BTI and its underlying subcomponents are studied. Physical origins of different TG and TP processes have been identified using Density Functional Theory (DFT) simulations.

Carrier transport in high mobility InAs nanowire junctionless transistors.

The impact of the gate insulator process on interlayer (IL) hole traps in IL/high-K dual-layer p-MOSFET gate-stack is studied by physical and electrical measurements along with atomistic simulations. Processes that lead to higher concentrations of Hf and N in IL, measured by angle-resolved X-ray photoelectron spectroscopy, result in higher IL hole traps measured by flicker noise in prestress and verified by atomistic simulations. The influence of these process induced preexisting IL hole traps on parametric degradation of p-MOSFETs during Negative bias temperature instability (NBTI) stress is studied. The mechanism responsible for superior NBTI of thermal IL stack, having lower Hf and N content in the IL as compared with Chem-Ox IL stack, is explained.

Trap Generation in IL and HK layers during BTI / TDDB stress in scaled HKMG N and P MOSFETs

A novel method to model the effect of local workfunction variation in high-k metal gate nanoscale transistors is proposed. Impact of variability in metal grain granularity on device performance is studied using ab initio density functional theory calculations and device simulations, which show that different metal grain orientations (GOs) can result in large (≥100 mV) variation in metal gate effective work function. Probabilities of occurrence of each GO and the grain size are used to estimate the work-function variations. Full 3-D device simulations are performed to study the effect of metal grain granularity on FinFET and planar MOSFET behavior. Simulated mismatch trends are shown to be in good agreement with the grain diameters and device geometries.

Understanding Process Impact of Hole Traps and NBTI in HKMG p-MOSFETs Using Measurements and Atomistic Simulations

Numerical modeling is used to explain the origin of the large ON/OFF ratios, ultralow leakage, and high ON-current densities exhibited by back-end-of-the-line-friendly access devices based on copper-containing mixed-ionic-electronic-conduction (MIEC) materials. Hall effect measurements confirm that the electronic current is hole dominated; a commercial semiconductor modeling tool is adapted to model MIEC. Motion of large populations of copper ions and vacancies leads to exponential increases in hole current, with a turn-ON voltage that depends on material bandgap. Device simulations match experimental observations as a function of temperature, electrode aspect ratio, thickness, and device diameter.

Ab initio Study of Metal Grain Orientation-Dependent Work Function and its Impact on FinFET Variability

We report experimental characterization and modeling of direct and trap-assisted tunneling (TAT) in high-K metal gate (HKMG)-based access transistor and deep trench (DT) capacitor constituting a 32 nm embedded dynamic random access memory (eDRAM) device. This is the first eDRAM technology that has successfully integrated HKMG-based access transistor and DT technology. The experimental results are compared with direct and TAT models implemented in a finite element-based device simulator. While in HKMG-based nFET both TAT, and direct tunneling are present, in the DT capacitor TAT is dominant due to higher interface and bulk traps. We demonstrate, through ab initio simulations, that the bulk and interface traps arise due to oxygen vacancies (Ov) in the bulk HfO2, and SiO2/HfO2 interface and quantitatively compare direct and TAT currents with experimental results.