Stephen S. Furkay

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors☆

Abstract A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, and ESD test data, will be shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25°C and is less than 400 fA per cell at 1.5 V, 85°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, ESD test data, and an ESD analytical failure model are shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs

The efficient and successful realization of low-power semiconductor devices demands, among other things, the ability to quantitatively model and minimize myriad leakage phenomena. We report herein a general physical model to quantitatively compute crystallographic-orientation-dependent gate-induced drain leakage (GIDL), and its numerical implementation in a continuum-based device simulator. This simulation model has been successfully compared with relevant experimental data derived from heavily doped vertical diodes and 45-nm silicon-based CMOS devices. Also, the process optimization of next-generation 32-nm low-power devices has been discussed in the context of GIDL.

THREE-DIMENSIONAL TRANSIENT ELECTROTHERMAL SIMULATION OF ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS

Abstract Transient electrothermal simulation of ESD protection circuits using the 3-D finite element device simulator will be shown to explain the electrothermal physics in ESD protection circuits in 0.5 and 0.25 μm channel length CMOS technologies. Simulation, ESD and failure analysis will be compared for evaluation of correlation.

Thermal characterization of plastic and ceramic surface-mount components

The thermal performance of devices packaged with the 68-, 84-, 100-, and 124-lead members of the plastic and ceramic flatpack family of surface-mounted components (PFP and CPF, respectively) is characterized. Experimental data were collected in both natural and force convection conditions for individual components surface-mounted to small sections of epoxy circuit card. Average air velocity and chip power dissipation were the primary independent test variables, ranging from 0 to 3 m/s and 0.2 to 2.0 W, respectively, for which internal and external thermal resistance data are presented. Experimental thermal resistance data exhibited the usual dependence on both Reynolds and Grashof numbers. Molding compound and leadframe materials were found by the model to have a significant effect on PFP thermal performance. Ceramic and die-attach materials were found to have significant and negligible effects, respectively, on thermal performance of the CFP package. >

Ab initio Study of Metal Grain Orientation-Dependent Work Function and its Impact on FinFET Variability

A novel method to model the effect of local workfunction variation in high-k metal gate nanoscale transistors is proposed. Impact of variability in metal grain granularity on device performance is studied using ab initio density functional theory calculations and device simulations, which show that different metal grain orientations (GOs) can result in large (≥100 mV) variation in metal gate effective work function. Probabilities of occurrence of each GO and the grain size are used to estimate the work-function variations. Full 3-D device simulations are performed to study the effect of metal grain granularity on FinFET and planar MOSFET behavior. Simulated mismatch trends are shown to be in good agreement with the grain diameters and device geometries.

Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using Ron-Lgate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.

Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM

We report experimental characterization and modeling of direct and trap-assisted tunneling (TAT) in high-K metal gate (HKMG)-based access transistor and deep trench (DT) capacitor constituting a 32 nm embedded dynamic random access memory (eDRAM) device. This is the first eDRAM technology that has successfully integrated HKMG-based access transistor and DT technology. The experimental results are compared with direct and TAT models implemented in a finite element-based device simulator. While in HKMG-based nFET both TAT, and direct tunneling are present, in the DT capacitor TAT is dominant due to higher interface and bulk traps. We demonstrate, through ab initio simulations, that the bulk and interface traps arise due to oxygen vacancies (Ov) in the bulk HfO2, and SiO2/HfO2 interface and quantitatively compare direct and TAT currents with experimental results.

TCAD study of back-gate biasing in UTBB

We have shown here a comprehensive set of results on the coupling factor in a UTBB technology based on TCAD simulation. An interesting result is the degree to which the coupling factor is not constant across the possible realistic range of biases, and that not only back-gate depletion may play a role, but fixed charges and work function variation change the behavior. This suggests that these dependencies may be used to characterize those important variables, and also indicates that use of the back-gate in circuit operation must take into account the variation in coupling factor across the practical operating range.