Rajarshi Saha

Packaging-compatible wafer level capping of MEMS devices

A cost-effective, wafer-level package process for microelectromechanical devices (MEMS) is presented. The movable part of MEMS device is encapsulated and protected while in wafer form so that commodity, lead-frame packaging can be used. A polymer epoxycyclohexyl polyhedral oligomericsilsesquioxanes has been used as a mask material to pattern the sacrificial polymer as well as overcoat the air-cavity. The resulting air-cavities are clean, debris-free, and robust. The cavities have substantial strength to withstand molding pressures during lead-frame packaging of the MEMS devices. A wide range of cavities from 20@mmx400@mm to 300@mmx400@mm have been fabricated and shown to be mechanically stable. These could potentially house MEMS devices over a wide range of sizes. The strength of the cavities has been investigated using nano-indentation and modeled using analytical and finite element techniques. Capacitive resonators packaged using this protocol have shown clean sensing electrodes and good functionality.

Design and fabrication of low-loss horizontal and vertical interconnect links using air-clad transmission lines and through silicon vias

In this paper we present the design and fabrication of air-clad planar transmission lines and TSVs that can be used as horizontal and vertical chip-chip interconnects. Performance improvement by using heterogeneous air-clad dielectric is presented for these two types of interconnect structures that establishes the basic motivation for fabricating these structures. The design data is verified by performing simulation using 3D full-wave solver HFSS. We outline the process flow for air-clad transmission lines and TSVs in detail. Several challenges in the fabrication of air-clad structures are also discussed.

Air cavity low-loss signal lines on bt substrates for high frequency chip-to-chip communication

Chip-to-chip communication across conventional printed circuit boards is limited to low frequencies (a few GHz), thus limiting the aggregate bandwidth without the use of optics. Low-loss, air insulated transmission lines can extend the frequency range of electrical circuitry on fiberglass-epoxy substrates (e.g. FR4 and BT). Described in this paper are electrical signal lines separated only by an airgap fabricated on BT substrates. The structures demonstrated greater than 46 percent reduction in capacitance and greater than 90 percent in loss tangent, which translates to substantially lower losses at high frequencies (10 GHz or greater). Attenuation in these structures have been simulated to be eight times lower than conventional microstrip lines. Air cavity signal lines are currently being integrated on multilayer BT substrates to demonstrate chip-to-chip communication using chips fabricated at the 65-nm node employing cross-talk cancellation techniques.

Air cavity low-loss transmission lines for high speed serial link applications

This paper reports on the design, optimization, processing and measurement of an air-cavity transmission line structure on FR-4 boards for high-speed chip-to-chip links. The proposed structure has air as the insulating material, thereby minimizing the dielectric loss. Full-wave electromagnetic simulation is used to predict the performance of the proposed air-cavity structure. Compared to conventional transmission lines on an FR4 substrate, the effective dielectric constant is reduced by 25% from 2.75 to 2.07, and the dielectric loss is reduced by 26% from 0.48 dB/cm (1.22 dB/inch) to 0.35 dB/cm (0.9 dB/inch) at 20 GHz. Simulation also shows that conductor surface roughness contributes significant loss, which is confirmed by the measurement results. An active low power electrical link demonstration is also reported herein. The transmitter (TX) utilizes a 1-tap feed-forward-equalization (FFE) for pre-cursor cancellation and the receiver (RX) a 1-tap decision-feedback-equalization (DFE) for post-cursor cancellation. The TX and RX frontends implement a current-sharing scheme to reduce the overall link power consumption. The circuitry and interconnect were co-designed to achieve 6.25 Gb/s at ∼0.6 mW/Gb/s (or 0.6 pJ/bits) in 0.13 μm 1.2V CMOS process.

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

In this study, we are pursuing an ultra low-loss interconnect pathway for 3D chip-chip connectivity, incorporating air-clad planar interconnects, air-clad TSVs, and gradual vertical-horizontal transitions. The motivation is to create an air-gap technology that offers the lowest possible effective k-value and near zero loss tangent minimizing the dielectric loss. The design and modeling of air-gap interconnection is presented. The fabrication challenges in air-clad interconnect lines are discussed. A monolithic inverted air-gap horizontal transmission line structure is proposed as a means for further decreasing the dielectric loss. Extension of air-clad TSV technology for optical transmission is briefly discussed.

Air Cavity Transmission Lines for Off-Chip Interconnects Characterized to 40 GHz

In this paper, air cavity transmission lines are integrated into printed circuit boards and packages to enable high-speed low-loss chip-to-chip communication. Microstripline and parallel plate structures with copper conductors separated by an air gap dielectric layer are described. The structures use a sacrificial placeholder material along with conventional microelectronics techniques to create a unique buried copper- air-copper microstripline structure. Transmission lines were characterized by S-parameter measurements to 40 GHz. The capacitance was tracked during fabrication to analyze the impact of the air gap. The effective dielectric constant of the final buried copper-air-copper structure was as low as 1.25.

Three dimensional air-gap structures for MEMS packaging

Air-gap structures are of interest in a range of microelectronic applications especially in microelectromechanical systems (MEMS). In this work, we investigate the application of an unique trimaterial for MEMS packaging composed of polypropylene carbonate (PPC) as a sacrificial material, a photosensitive, hybrid inorganic/organic dielectric epoxycyclohexyl polyhedral oligomeric silsesquioxanes (POSS) as the overcoat material, and Al/Cr-Cu thin metal film as a hermetic seal. POSS was used both for patterning the PPC over the structures as well as a stable overcoat material thus reducing the complexity of the fabrication process. A wide range of device sizes and structures (from 20 × 100 µm to 600 × 1000 µm) were fabricated and the processing protocol was found to be compliant over these size/structure variations. Metal adhesion on the overcoat was substantially improved by using low power oxygen plasma for short durations. Cavity-strength was evaluated for different metals and thicknesses. An increase of 5.6 times in cavity-strength was observed for a thicker (3X) Al metal film. Current work is focused on implementing the wafer-level air-cavity package into a lead frame packaged MEMS device through injection and compression molding techniques.