Rajen Dias

Electro Optical Terahertz Pulse Reflectometry — an innovative fault isolation tool

Electro Optical Terahertz Pulse Reflectometry (EOTPR), an innovative time domain reflectometry (TDR) system, has been successfully developed. This is the first system that applies terahertz technology to time domain reflectometry. The system has achieved 10 um resolution, 5.7ps rise time, 94dB signal/noise ratio and 150 mm testing range and it has been successfully integrated into fault isolation and failure analysis process flow.

Acoustic evaluation of electronic plastic packages

Describe a technique of C-mode scanning acoustic microscope (CSAM) image acquisition. The role acoustic reflected wave analysis plays in the acquisition of CSAM images is considered. The effect that mold compound thickness and transducer choice have on the resolution of leadframe features in plastic packages is illustrated. Potential applications of acoustic reflected wave analysis are presented.<<ETX>>

Lead-Free Solder Joint Void Evolution During Multiple Subsequent High-Temperature Reflows

Entrapment of volatiles during lead-free solder joint formation results in the creation of voids which may have a negative impact on the joints mechanical and/or electrical performances. According to IPC-J-STD-001E and IPC-A-610E specifications, the post-surface-mount-technology cumulative voiding criterion in lead-free solder joints is less than 25% for a second-level interconnect. For solder joints that experience multiple high-temperature reflow processes after completion of assembly, however, it is important to understand and predict how these voids will interact and evolve during subsequent high-temperature exposures. In this paper, both in situ 2-D X-ray imaging and 3-D X-ray tomography were used to study the growth kinetics of solder joint voids during multiple reflow cycles. The results demonstrate that voids grow and move during each reflow cycle. The growth kinetics has been shown to follow a diffusion-controlled mechanism based on a model for out-gassing bubble growth in a supersaturated molten solder liquid.

Investigation of interfaces with analytical tools

This paper focuses on advancements in three areas of analyzing interfaces, namely, acoustic microscopy for detecting damage to closely spaced interfaces, thermal imaging to detect damage and degradation of thermal interface materials and laser spallation, a relatively new concept to understand the strength of interfaces. Acoustic microscopy has been used widely in the semiconductor assembly and package area to detect delamination, cracks and voids in the package, but the resolution in the axial direction has always been a limitation of the technique. Recent advancements in acoustic waveform analysis has now allowed for detection and resolution of closely spaced interfaces such as layers within the die. Thermal imaging using infrared (IR) thermography has long been used for detection of hot spots in the die or package. With recent advancements in very high-speed IR cameras, improved pixel resolution, and sophisticated software programming, the kinetics of heat flow can now be imaged and analyzed to reveal damage or degradation of interfaces that are critical to heat transfer. The technique has been demonstrated to be useful to understand defects and degradation of thermal interface materials used to conduct heat away from the device. Laser spallation is a method that uses a short duration laser pulse to cause fracture at the weakest interface and has the ability to measure the adhesion strength of the interface. The advantage of this technique is that it can be used for fully processed die or wafers and even on packaged devices. The technique has been used to understand interfaces in devices with copper metallization and low-k dielectrics.

Rapid die heating for low-stress die attach

During traditional isothermal die attach assembly, significant thermomechanical stress develops in the solder joints between the die and board. The coefficient of thermal expansion (CTE) of the silicon die and the woven composite circuit board materials are widely different. Under isothermal die attach, there is, hence, a mismatch between the thermal expansion displacements of the die and substrate, thereby leading to stress in the solder joints and die interconnect layers. One avenue to alleviate these stresses is to use alternate die attach processes that rely on localized heating of the die and solder joints so as to minimize the thermal expansion displacement mismatch. Die attach stress can be reduced significantly through rapid die heating (RDH), which results in the die being hotter than the board at the solder solidification point. Analytical modeling shows that RDH can reduce residual stress by up to 80% compared to traditional, isothermal die attach processing. Limited experimental results demonstrate 40% stress reduction to date. This paper will detail these results and physical analysis of the resulting solder joints.

Laser-based sample preparation for electronic package failure analysis

Failure analysis has come to play a key role in ensuring quality and reliability in semiconductor devices, associated packaging and printed wiring boards. Tools are increasingly available to those investigating high-density integrated circuits at the die level, particularly for edit and repair operations. Until recently however, this capability has been limited by the inherent low-resolution mechanical/manual processes used for destructive analysis on electronics packaging. A laser-based tool has been developed to selectively and locally enable access to traces and layers within packages and provide a way to perform edits to an area of interest.

Analytical challenges in next generation packaging/assembly

Next generation assembly/package development challenges are primarily thermal mechanical as interconnect levels increase and product performance drives the need for increased speed and power dissipation. The results of this trend present some distinct challenges for the analytical tool/technique set necessary to support this technical roadmap. The challenges in assembly analytical tool/technique development are in the areas of nondestructive imaging, board level fault isolation and materials property measurement to model and validate the thermal mechanical response of the assemblage. The purpose of this paper is to review the likely defects in next generation packages and the analytical approaches to identify these defects.

Pressure-Compensated Chip Attach: A Low-Stress Silicon Bump Reflow Process

Assembly of silicon onto FR4-based organic substrates using flip-chip process continues to pose substantial thermomechanical challenges largely due to the disparate coefficients of thermal expansion (CTEs) of silicon and substrate. In flip-chip packaging, this CTE mismatch causes mechanical stresses in the chip-to-substrate interconnection bumps and the mechanically fragile interlayer dielectric (ILD) within the chip, leading to fracture and delamination. A novel process called pressure-compensated chip attach (PCCA) is presented, where the silicon chip is attached to the substrate by reflowing the solder bumps while maintaining the chip and substrate in a controlled hydrostatic pressure environment. Experiments show that the new PCCA process reduced the silicon test-chip warpage by 40% and eliminated ILD cracking.

The mechanism and kinetic study of void migration in Cu vias under current flow by 3D X-ray computed tomography

Miniaturization and portability of consumer electronics is driving the substrate technology to enable packages with higher circuit density, smaller size, and lower Z height. Cu vias with large aspect ratio are being used for these next generation substrate technologies. Due to the relatively large aspect ratio of the Cu vias, voids could form during the electrolytic Cu filling process. To understand the void behavior under current flow, samples are subjected to high current at elevated temperatures. 3D X-ray computed tomography is used to characterize these voids in Cu vias before and during the test at intermediate readouts. These studies find that the voids accumulate and migrate preferentially to the applied bias polarity. The hypothesis of the void movement under current flow is discussed and the kinetics of the void migration is proposed with the estimations of activation energy and current density exponent.

The assembly analytical forum: Addressing the analytical challenges facing packaging and assembly

Many factors are coming together simultaneously, pushing current fault isolation and failure analysis methods to their limits. Greater numbers of differentiated products are emerging in shorter timeframes in a greater variety of packages, while at the same time incorporating significantly different materials, smaller geometries, and improved thermal performance at both the die and package level. This makes it more important than ever before to have test methods that quickly isolate a problem to the die or package level. A particular challenge is the analysis of fully enabled assemblies (including thermal performance options such as heat exchangers and thermal slugs; retention modules; EMI shielding; and on-board inspection). Without forecasting, the required assembly and packaging analysis tools will not be available when needed. Thus, the Sematech Assembly Analytical Forum (AAF) was formed in 1999 to focus on techniques and tools that uniquely impact packaging, to highlight the critical analytical breakt...