Biju Chandran

An accelerated reliability test method to predict thermal grease pump-out in flip-chip applications

In packages using thermal grease as the conducting medium between the die and the thermal solution, grease pump-out during operation of the part is a known failure mechanism. Traditional power cycle test is a direct method to examine grease reliability. However, it is a time consuming process due to its long heating and cooling times. In order to screen numerous thermal grease materials during the initial design phase of a microprocessor package, it is advantageous to utilize a quick turn test. This paper describes an accelerated mechanical test, developed to evaluate interface degradation, due to pump-out. An MTS(R) universal testing machine is used to simulate the squeezing action on the grease, caused by die warpage change. By using this accelerated testing method, product design cycle time can be significantly reduced. In this paper, a silicone-oil-based AlN-filled thermal grease with different thickness at the corresponding device operation temperature is examined by using this accelerated test method. Results from this test are also compared to traditional power cycle test results.

Effect of package design and layout on BGA solder joint reliability of an organic C4 package

Ball Grid Array (BGA) is currently the interconnect of choice for attaching microprocessors on a printed circuit board (PCB). The reliability of solder joints is one of the critical issues in BGA surface mount technology (SMT). During reliability testing, BGA fatigue failures were observed on test vehicles (TV). Finite element analysis and physical failure analysis were used to determine the risk to the product in the field. As part of this effort, parametric finite element analysis was carried out to determine the effect of design features like the package size, and BGA pattern on the propensity of fatigue failure. The results of the finite element analysis and physical failure analysis showed that the risk to fatigue failure was much greater on a peripheral/partial grid array package than in a full grid array package.

On Measurement of Effective Silicon Backend Strength Using Bump Pull/Shear Techniques

Integrating a low-K ILD layer within silicon is key to reducing RC delays. However, low-K ILD materials typically have low mechanical strength, making their incorporation with lead free interconnects an industry-wide challenge. It is well known that conversion to lead free first level interconnects increases die backend stresses due to the higher melting temperature and increased solder stiffness. The paper will focus on the measurement of the effective silicon backend strength after subjecting the dice to different fabrication and assembly steps. The effective strength will also be evaluated post reliability stress exposure to eventually understand the life of these films. The paper will describe how a commercially available Dage 4000 tool was modified for this application. Bump pull was carried out using a 100μm tweezers, while bump shear used 1mil (25.4μm) wide stylus. Static and dynamic calibration was first carried out to ensure repeatability and reproducibility of the results. Peak force and failure modes were used as metrics to compare the effectiveness of different experimental legs. Traditional failure analysis approach of mechanical polishing, or when needed, use of FIB for sample preparation, with subsequent SEM/EDX analysis was utilized to understand the failure mechanism. Data suggests that shear and pull lead to different failure modes. Bump shear mainly led to failure at the bump/polyimide interface and did not necessarily correspond to the weakest layer or interface in the silicon backend. Whereas bump-pull, which applies tensile force to the stack up, lead to failures in the weakest layer, typically the low-K ILD, in the silicon backend. Hence, bump pull provided the advantage over shear as it allowed evaluation of the weakest interface in the stack up. Two case studies are discussed to demonstrate on how bump pull/shear metrologies were used to understand the impact of different assembly/FAB process variables and highly accelerated steam test (HAST) reliability stress on silicon backend strength. First case study shows influence of assembly flux on silicon backend strength, while second case study describes impact of HAST on different FAB backend processes.Copyright

Test vehicle to characterize silicon to organic flip chip package thermomechanical interactions

The thermomechanical interaction of organic flip chip assembly is primarily driven by the coefficient of thermal expansion (CTE) mismatch between die and package. This, in addition to emerging constraints like mechanically weaker silicon inter-layer dielectrics, lead free assembly and tighter bump pitch, etc., significantly increase the assembly yield and reliability challenges. Electrically sensitive short loop assembly test vehicles with representative product design features provide quick data turn and more coverage than live products to address these interconnect concerns. Yield and reliability data plus stress modeling and experimental measurements from assembly test vehicles highlight the importance of silicon and package test structures to understand die to package CTE mismatch induced stress, helping to identify the weak links in packaging architecture from materials, process and design.

Exploring the Possibility of Approximating Viscoelastic Response of Underfill Materials Through the Use of Appropriate Linear-Elastic Material Models

Viscoelastic analysis for numerical modeling of IC assembly processes are generally non-linear and require extensive time and computational resources when compared to a linear elastic analysis. Experimental identification/approximation of the viscoelastic properties (in terms of the Prony series) of any polymeric material is also an exhaustive effort. These drawbacks in experimental procedures and modeling activities have forced us to explore the possibility of approximating viscoelastic response of a polymer with an appropriate linear-elastic model. This paper discusses the impact of different approximation methodologies for a viscoelastic material most commonly used in electronic packaging — the underfill material in flip-chip technology. The modeling methodologies discussed here include the use of long term modulus, short term modulus and other “effective” stiffness measures to approximate the response of underfills during assembly processes. The package response, from each of these models, has been compared to the package response from a linear viscoelastic analysis assuming underfill materials to behave as Maxwell solids. It has been observed that the short term modulus consistently over predicts the ILD (interlayer dielectric in the silicon backend) peel stress for various underfill materials. In addition, the paper also explores the existence of an “effective” stiffness that can be used in lieu of a full fledged viscoelastic analysis. The ability to estimate this “effective” stiffness using available temperature dependent modulus data (from DMA tests) is also discussed. The applicability of this effective metric to different underfill materials has also been explored. In conclusion, this study highlights the need for accurate characterization of polymeric materials so that numerical predictions can provide realistic risk assessments for future packaging technologies.Copyright

Challenges in thermo-mechanical failure prediction of electronic packages

Early discovery of potential failure modes, and understanding their sensitivity to critical design parameters is critical to any organization involved in electronic packaging. Typically mechanical simulation are used for this purpose. Some of the recent changes - low K ILDs (interlayer dielectrics) and lead free interconnects have introduced new challenges while increased the importance of modeling. Predicting failure in the porous ILD material introduce many challenges. In the case of lead free solders, in addition to the need to understand the fatigue characteristics of these materials, the impact of the resulting higher reflow temperatures on other packaging material must also be studied. Typical modeling techniques are very effective as a comparative tool - i.e. to compare amongst various designs for any particular failure mode.