Colin T. Carver

Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process

A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.

Resistance and electromigration performance of 6 nm wires

A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements showing line electrical resistance and electromigration as functions of material, conducting area, and interfaces are presented.

Simple test vehicle for metal fill and resistance of sub-8nm nanowire

Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabricated with existing silicon patterning recipes to achieve an electrical test vehicle that can test a range of metal candidates for interconnects. The vehicle is characterized using electron microscopy and electrical measurements.

Demonstration of a sidewall capacitor to evaluate dielectrics and metal barrier thin films

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.

Nickel silicide for interconnects

Nickel silicide is an attractive option for interconnects at small dimensions because of its short electron mean free path and good electromigration behavior. Nickel silicide interconnects can be integrated using either a subtractive or damascene process. Precise control of final metal composition ratio is important for obtaining low resistivity, as shown in thin-film and patterned structure measurements.