Raminderpal Singh

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices

This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in D. Goren et al. (2002), into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T-line) devices for the critical interconnects, which is expanded to include coplanar structures while considering the silicon substrate effect. The generalized methodology contains treatment of the crossing line effects at the various design stages, including two way interactions between the post layout extraction tool and the T-line devices. The T-line device models are passive by construction, easily migratable among design environments, and allow for both time and frequency domain simulations. These models are verified by S-parameter measurements up to 110GHz, as well as by EM solver results. It is experimentally shown that the effect of properly designed discontinuities is negligible in most practical cases. The basic on-chip T-line methodology is being used extensively for numerous high-speed designs.

RFCMOS technology from 0.25/spl mu/m to 65nm: the state of the art

The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS, focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools, using which, designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.

Design and fabrication of a prototype projection data monitor with high information content

A prototype 28-in.-diagonal desktop data monitor capable of displaying 2048 × 2048- pixel images has been designed, built, and evaluated. The monitor uses optical projection technology. A reflective, crystalline silicon active-matrix light valve using liquid crystal electro-optics and a digital electronic interface architecture is described. This rear-projection monitor has four million resolvable pixels, uses three light valves to achieve color, has a low-gain surface diffuser screen, and functions as a fully interactive, color personal computer monitor with motion video capability. The monitor is 20 in. deep.

Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies

The rapidly expanding telecommunications market has led to a need for advanced rf integrated circuits. Complex rf- and mixed-signal system-on-chip designs require accurate prediction early in the design schedule, and time-to-market pressures dictate that design iterations be kept to a minimum. Signal integrity is seen as a key issue in typical applications, requiring very accurate interconnect transmission-line modeling and RLC extraction of parasitic effects. To enable this, IBM has in place a mature project infrastructure consisting of predictive device models, complete rf characterization, statistical and scalable compact models that are hardware-verified, and a robust design automation environment. Finally, the unit and integration testing of all of these components is performed thoroughly. This paper describes each of these aspects and provides an overview of associated development work.

Parasitic modeling and noise mitigation in advanced RF/mixed-signal silicon germanium processes

The potential for highly integrated radio frequency (RF) and mixed-signal (AMS) designs is today very real with the availability cost-effective scaled silicon-germanium (SiGe) process technologies. However, the lack of effective parasitic modeling and noise mitigation significantly restrict opportunities for integration, due to a lack of computer-aided design solutions and practical guidance for designers. This tutorial paper provides a broad in-depth coverage of the key technical areas that designers need to understand in estimating and mitigating IC parasitic effects. A detailed analysis of the parasitic effects in passive devices, the interconnect (including transmission line modeling) and substrate impedance, and isolation estimation is presented-referencing a large number of key publications in these areas.

Vertically-stacked on-chip SiGe/BiCMOS/RFCMOS coplanar waveguides

This paper presents a new on-chip transmission line interconnect structure which offers the potential of superior return and insertion loss characteristics compared to the equivalent standard transmission line device. Conventional on-chip coplanar waveguides (CPW) and differential pairs are routed in a single metal layer in the chips metal-dielectric stack. The vertically stacked coplanar waveguide (PW) transmission lines presented here consist of metal lines on multiple metal levels connected by continuous via bars. The additional cross-sectional area of the VCPW topology decreases interconnect resistance while the increased effective device thickness increases capacitance to neighboring ground return lines leading to a characteristics impedance reduction.

Integrated SiGe and Si device capabilities and trends for multi-gigahertz applications

Silicon-based devices, including the increasingly available SiGe-based devices, are now demonstrating fT and fMAX values over 200 GHz. These recent advances open the door to a wide range of silicon-based very high frequency, low power and highly integrated solutions. Trends in silicon MOS, SiGe HBT, SiGe MODFET and SiGe strained silicon FETs are reported. Silicon inroads to device functions viewed as the sole realm of III-V technologies are also being demonstrated. Capability and trends of the integrated silicon photodiode are reported here as an example. Integration of these high-speed devices into a complex circuit requires on-chip passive device functionality at such high frequency. Key devices to enable integration are the inductor, varactor, and transmission line, and operation of these devices at high frequency is reported. Further, we discuss noise isolation issues and techniques, which may be used when minimizing cross-talk within a conductive silicon substrate.

Design Automation and Signal Integrity

Chapter 3 discusses the enablement involving best-in-class design automation solutions - including the CAD tools environment, RF simulation algorithms, ESD CAD solutions, and signal integrity solutions for interconnect and substrate modeling. These offerings form together with the compact models, to form the design enablement for the customer. As such they are complex software engineering projects requiring very high quality and efficiency, and in the case of signal integrity the need for effective and efficient modeling usable by the design community. The chapter overviews the IBM design automation methodology, the ESD design automation offering, interconnect modeling requirements and solutions, and substrate isolation and modeling solutions. Key points brought out in this chapter include: Overview of IBMs design automation methodology. Discussion of the design automation environment for IBMs world-class ESD offering. Introduction to the complex topic of interconnect modeling and extraction, including transmission line modeling and substrate interactions to interconnects. Discussion of issues in substrate modeling and isolation, through co-ordinated TCAD and test-site activities at IBM. ]]>