Salomon Beer

Temperature sensitivity of SOI-CMOS transistors for use in uncooled thermal sensing

The temperature coefficient of current (TCC) of CMOS transistors implemented on silicon-on-insulator substrates is theoretically and empirically studied for its potential use in uncooled thermal sensing. Modeling and measurements show TCC values in subthreshold of more than 6%/K, better than state of the art microbolometer temperature coefficient of resistance, and less than -0.4%/K in saturation-comparable with metals. Models and measurements are shown for the TCC dependence upon operating point, temperature and channel length. A simple semi-empirical model for the TCC at subthreshold based on long channel approximation is suggested and shown to agree with measurements for channel length down to 0.35 /spl mu/m. The model and measurements show a logarithmic tradeoff between subthreshold current and the TCC, which is important in the design of sensors.

MTBF Bounds for Multistage Synchronizers

Synchronizers are used to mitigate the effects of metastability in multiple clock domain System-on-Chip devices. In order to enable reliable synchronization, the synchronizer MTBF (Mean Time Between Failures) should be much longer than the product lifetime. To achieve such high margins, multistage synchronizers are used. Several simulation methods have been developed to determine their probability of failure and the number of stages to use. While simulation methods have improved in recent years, accurate analytical models for failure calculations are scant. Some previously published models do not reflect estimations of MTBF but only loose lower bounds that give rise to a high number of synchronizer stages reducing the overall system performance. Others provide improved accuracy but are difficult to operate and simulation for each stage is required. In this paper, we review published analytical models for MTBF calculations of multistage synchronizers. We show that existing models often underestimate MTBF, and in some cases they even overestimate it. A new model that calculates a MTBF lower bound with significantly smaller margins is introduced. These estimates are shown to be consistent with state of the art simulations and measurements. A method for calculating these estimates for a variety of applications is presented based on a limited number of intrinsic synchronizer parameters determined by simulation.

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm circuits and beyond. An on-chip metastability measurement circuit was fabricated in a 65nm 1.1V bulk CMOS. A fully digital on-chip measurement system is presented here that helps to characterize synchronizers in future technologies. Different types of synchronizers were measured and compared. The standard library FF is demonstrated to have lower tau value than various feedback flip-flops.

Metastability in Better-Than-Worst-Case Designs

Better-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster than the one required for worst-case conditions. This speculation may produce timing violations and metastability that result in failures and non-deterministic timing behavior. The effects of these phenomena are not always well understood by designers and researchers in this area. This paper analyzes the impact of timing speculation and the reasons why it is difficult to adopt this paradigm in industrial designs.

Metastability challenges for 65nm and beyond: simulation and measurements

Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and below. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system is shown that accounts for changes in delay values due to supply voltage and temperature changes. We present a detailed comparison of measurements and simulations for a fabricated 65nm bulk CMOS circuit and discuss implications of the measurements for synchronization systems in 65nm and beyond. We propose an adaptive self-calibrating synchronizer to account for supply voltage, temperature, global process variations and DVFS.

Eleven Ways to Boost Your Synchronizer

Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimumVTH, overprovisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.

MTBF Estimation in Coherent Clock Domains

Special synchronizers exist for special clock relations such as mesochronous, multi-synchronous and ratiochronous clocks, while variants of N-flip-flop synchronizers are employed when the communicating clocks are asynchronous. N-flip-flop synchronizers are also used in all special cases, at the cost of longer latency than when using specialized synchronizers. The reliability of N-flip-flop synchronizers is expressed by the standard MTBF formula. This paper describes cases of coherent clocks that suffer of a higher failure rate than predicted by the MTBF formula, that formula assumes uniform distribution of data edges across the sampling clock cycle, but coherent clocking leads to drastically different situations. Coherent clocks are defined as derived from a common source, and phase distributions are discussed. The effect of jitter is analyzed, and a new MTBF expression is developed. An optimal condition for maximizing MTBF and a circuit that can adaptively achieve that optimum are described. We show a case study of metastability failure in a real 40nm circuit and describe guidelines used to increase its MTBF based on the rules derived in the paper.

An extended metastability simulation method; Extended node short simulation (ENSS)

Synchronizers play a key role in multi-clock domain systems on chip. One of the essential points in designing reliable synchronizers is to estimate and evaluate synchronizer parameters and Typically, evaluation of these parameters has been done by empirical rules of thumb or simple circuit simulations to ensure that the synchronizer MTBF is sufficiently long. This paper shows that those rules of thumb and some common simulation method are unable to predict correct synchronizer parameters in deep sub-micron technologies. We propose a new simulation method to estimate synchronizer characteristics more reliably and compare the results obtained with other state of the art simulation methods. Simulation results for each of the analyzed methods are compared with measurements of a 65nm LP CMOS test-chip.

Variability in Multistage Synchronizers

System-on-a-chip designs typically employ multiple clock domains to interface several externally clocked circuits operating at different frequencies and to reduce power and area by breaking large clock trees into multiple small ones. The principal challenge of such globally asynchronous locally synchronous architectures is the need to reliably communicate between the different clock domains. To achieve high reliability margins in high-frequency designs implemented in modern process technologies, multistage synchronizers are often used. In this paper, we develop analytical formulas to calculate the probability of failure and the number of stages to use in such synchronizers. We compare our model with those reported in previous publications and show that most existing models underestimate mean time between failures (MTBF). Our model calculates an MTBF lower bound with significantly smaller margins. The concept of an effective resolution time constant for multistage synchronizers is introduced and the important effects of clock duty cycle and process variability are addressed. These process variability effects can be minimized by use of simple design rules for the synchronizer. For safety-critical applications, calculation of the probability of a failure-free lifetime for all products in a production run is developed and a simple lower bound is derived.

A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance

Synchronizers play a key role in multiclock domains systems on chip and their performance is usually measured by the mean-time between failures (MTBF) of the system. Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling for library flip-flop circuits in 65 nm and below. This degradation of parameters becomes critical when the system is operated under extreme supply voltage and temperature conditions. In this paper, we study the behavior of synchronizers in a broad range of supply voltage and temperature conditions. A new model for the metastability time constant (τ), the metastability window (TW), and MTBF is presented. We show a detailed comparison of model, measurements, and simulations for different technology nodes and discuss implications for modern synchronization systems. We propose design guidelines that account for supply voltage and temperature variations and determine the correct number of synchronizer stages required for target MTBF.