Xusheng Wu

Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET

The effects of nonrectangular fin cross section of double-gate FinFETs are studied. For a given top-fin width, which is defined by the photolithography step, the short-channel effect immunity is degraded by the inclination of the sidewalls. The nonrectangular fin geometry also leads to nonuniform current flow and current crowding in the vertical direction. Together with the nonuniform series resistance along the height of the fin, a nonlinear dependence of on-current with fin heights (which have been regarded as the Ws in planar MOSFET) is observed. The impacts of nonvertical sidewall have been characterized according to the inclination angle in this work. Under different inclination angles as dictated by the processing technology, the device performances at various fin heights are characterized. A new design constraint that limits the choice of fin height for a given technology is also discussed.

A stacked CMOS technology on SOI substrate

A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.

3-Dimensional Integration for Interconnect Reduction in for Nano-CMOS Technologies

This paper describes a method to integrate non-planar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis

A three-dimensional stacked fin-CMOS technology for high-density ULSI circuits

In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized.

Stacked 3-D Fin-CMOS technology

A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.

Three-dimensional stacked-Fin-CMOS integrated circuit using double layer SOI material

In this work, a stacked 3D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2D architecture; (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2D CMOS technology. To implement the 3D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.

A Capped Trimming Hard-Mask Patterning Technique for Integration of Nano-Devices and Conventional Integrated Circuits

Capped trimming hard-mask (CTHM) patterning technique has been developed based on standard materials and processing equipments. By using the CTHM technique, sub-50nm feature sized pattern can be realized based on 0.5μm lithography technology. Imaging layer for capping and hard-mask layer shoul d have different etching selectivity and good contiguity to each other. Good control of trimming etching and hard-mask etching processes enable patterning of features with ultra-small dimension.

Three dimensional analytical subthreshold model for non-rectangular cross-section FinFETs

The subthreshold characteristics of FinFETs with non-rectangular fin cross-section are investigated using evanescent-mode analysis. A three-dimensional analytical subthreshold conduction model is developed by applying the superposition principle to a two-dimensional model for ideal rectangular structures. The results from the analytical model are compared to three-dimensional numerical device simulations with good agreement. The model can be used to predict fabrication technology requirement in the scaling of a realistic nano-scaled FinFETs.