Yuncheng Song

3-D simulation of geometrical variations impact on nanoscale FinFETs

Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness (LER) and oxide thickness fluctuations (OTF). A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs performance. In this work, roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The influence of different geometrical variation sources is compared and summarized. The results shows that FinFETs performance is most sensitive to the fin LER, which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect (DIBL) and leakage current. The impact of gate LER follows that of fin LER. The simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.

Evaluating the effects of physical mechanisms on the program, erase and retention in the charge trapping memory

In this work, a new efficient simulation method with comprehensive physical models is developed to evaluate the performance of CTM at various biases, temperatures, and gate stack configurations. The dominant physical mechanisms on the P/E/R operations of CTM are clarified.

Monte Carlo Simulation of Band-to-Band Tunneling in Silicon Devices

A band-to-band tunneling model including trap-assisted tunneling has been implemented in our ensemble full band Monte Carlo simulator. Four kinds of band-to-band tunneling mechanisms are taken into account. All the parameters in the band-to-band tunneling model are verified by comparing the pn junction reverse current with the experimental data. Then, gate-induced-drain-leakage currents caused by band-to-band tunneling in a 45 nm gate length n-metal–oxide–semiconductor field-effect-transistor are investigated. Results indicate that band-to-band tunneling can cause additional hot holes which becomes an important issue for the device reliability. Moreover, The gate-induced-drain-leakage currents caused by band-to-band tunneling in parallel with Si/SiO2 interface and normal to Si/SiO2 interface are compared. The influence of drain voltage on the two components of the gate-induced-drain-leakage currents is considered.

Simulation of flash memory including charge trapping and de-trapping by Monte Carlo method

We propose a self-consistent method to simulate charge trapping and de-trapping in charge storage layer and its interfaces of SONOS type flash memory devices. This method can be used under various applied voltages; in various structures composed of multiple material, thickness and shape of gate stack layers. It can also work with arbitrary trap density distribution in either real space or energy space. Further more, the self-consistent method has enough flexibility to accommodate detailed physical models

Characteristics of sub-100nm ferroelectric field effect transistor with high-k buffer layer

The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100 nm ferroelectric field effect transistor (FeFET) with high-k material as the buffer layer. Different configurations of gate stack are simulated and analyzed. It is shown that the structure of double-layer buffer can improve the device performance efficiently. Some important issues for FeFET scaling down are also discussed in this paper.

Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs

Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.

Simulation of charge trapping memory with novel structures

The floating gate type of flash memory is impossible to scale down to beyond 45 nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio. Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping memory (CTM). CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. The NAND HC-TANOS flash cell has been generated in three dimensional TCAD tools with 38 nm gate length, 34 nm channel width and charge trapping structures. A structure of Al2O3 (15 nm)/Si3Na (6.5 nm)/SiO2 (4.5 nm) with TaN gate was employed as the gate stack. To study the effects of gate stack coverage on flash cells performance, the shape of gate stack is varied while keeping all other structural parameters fixed.

Local accumulated free carriers in charge trapping memory

The effects of local accumulated free carriers on CTM cells performance are investigated by numerical simulation. Simulation results indicates that local accumulated free carriers do not affect programming and erasing characteristic, however, they are important to CTMs retention characteristic, especially in low threshold state. For CTM cell with thick tunneling oxide and shallow trap depth in charge storage layer, absence of accumulated carriers will underestimate retention capability considerably.