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Dive into the research topics where Catherine B. Labelle is active.

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Featured researches published by Catherine B. Labelle.


Proceedings of SPIE | 2015

Plasma etch challenges with new EUV lithography material introduction for patterning for MOL and BEOL

Changwoo Lee; Bhaskar Nagabhirava; Michael Goss; Peng Wang; Phil Friddle; Stafan Schmitz; Jian Wu; Richard Yang; Yann Mignot; Nouradine Rassoul; Bassem Hamieh; Genevieve Beique; Andre Labonte; Catherine B. Labelle; John C. Arnold; John Mucci

As feature critical dimension (CD) shrinks towards and beyond the 7nm node, patterning techniques for optical lithography with double and triple exposure will be replaced by EUV patterning. EUV enables process and overlay improvement, as well as a potential cost reduction due to fewer wafer passes and masks required for patterning. However, the EUV lithography technique introduces newer types of resists that are thinner and softer compared to conventional 193nm resists currently being used. The main challenge is to find the key etch process parameters to improve the EUV resist selectivity, reduce LER and LWR, minimize line end shrink, improve tip-to-tip degradation, and avoid line wiggling while still enabling previous schemes such as trench-first-metal-hard-mask (TFMHM), self-aligned via (SAV) and self-aligned contact (SAC). In this paper, we will discuss some of the approaches that we have investigated to define the best etch process adjustments to enable EUV patterning. RF pulsing is one of the key parameters utilized to overcome most of the previously described challenges, and has also been coupled with stack optimization. This study will focus on RF pulsing (high vs. low frequency results) and bias control (RF frequency dependence). In particular, pulsing effects on resist morphology, selectivity and profile management will be reported, as well as the role of aspect ratio and etch chemistry on organic mask wiggling and collapse. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.


Advanced Etch Technology for Nanopatterning VII | 2018

Introduction of pre-etch deposition techniques in EUV patterning

Xun Xiang; Andre Labonte; Catherine B. Labelle; Bhaskar Nagabhirava; Phil Friddle; Stefan Schmitz; Michael Goss; Dominik Metzler; John C. Arnold; Genevieve Beique; Lei Sun

The thin nature of EUV (Extreme Ultraviolet) resist has posed significant challenges for etch processes. In particular, EUV patterning combined with conventional etch approaches suffers from loss of pattern fidelity in the form of line breaks. A typical conventional etch approach prevents the etch process from having sufficient resist margin to control the trench CD (Critical Dimension), minimize the LWR (Line Width Roughness), LER (Line Edge Roughness) and reduce the T2T (Tip-to-Tip). Pre-etch deposition increases the resist budget by adding additional material to the resist layer, thus enabling the etch process to explore a wider set of process parameters to achieve better pattern fidelity. Preliminary tests with pre-etch deposition resulted in blocked isolated trenches. In order to mitigate these effects, a cyclic deposition and etch technique is proposed. With optimization of deposition and etch cycle time as well as total number of cycles, it is possible to open the underlying layers with a beneficial over etch and simultaneously keep the isolated trenches open. This study compares the impact of no pre-etch deposition, one time deposition and cyclic deposition/etch techniques on 4 aspects: resist budget, isolated trench open, LWR/LER and T2T.


Archive | 2013

Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer

Gunter Grasshoff; Catherine B. Labelle


Archive | 2014

DUAL-STRAINED NANOWIRE AND FINFET DEVICES WITH DIELECTRIC ISOLATION

Yi Qi; Catherine B. Labelle; Xiuyu Cai


Archive | 2012

Formation of FinFET gate spacer

Douglas J. Bonser; Catherine B. Labelle


Archive | 2012

Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques

Sohan Singh Mehta; Tong Qing Chen; Vikrant Chauhan; Ravi Prakash Srivastava; Catherine B. Labelle; Mark Kelling


china semiconductor technology international conference | 2011

Plasma Etch Challenges for Porous Low k Materials for 32nm and Beyond

Catherine B. Labelle; Ravi Prakash Srivastava; John C. Arnold; Yunpeng Yin; Masao Ishikawa; Yann Mignot; Hakeem Yusuff; Joseph Linville; David V. Horak; Nicholas C. M. Fuller; Ryan Patz; A. Darlak; Kevin Zhou; Yifeng Zhou


Archive | 2016

METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Min Gyu Sung; Catherine B. Labelle


Archive | 2014

RAISED FIN STRUCTURES AND METHODS OF FABRICATION

Yi Qi; Xunyuan Zhang; Catherine B. Labelle


Archive | 2016

METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE

Gunter Grasshoff; Catherine B. Labelle

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