Rudolf Theoderich Bühler

Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (AV), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Fin shape influence on the analog performance of standard and strained MuGFETs

From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner Wmid there is a performance increase of up to 3 dB on intrinsic voltage gain compared to rectangular shape. Strained devices present better AV and fT, both following the gm tendency for each channel length.

Biaxial + uniaxial stress effectiveness in tri-gate SOI nMOSFETs with variable fin dimensions

MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is work we study the stress distribution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through electrical characterization of experimental devices and 3D process and device numerical simulation. Experimental results of standard and strained devices were used to validate the simulations. The bi+uni stress technique delivered enhanced maximum transconductance.

Fin width influence on uniaxial stress of triple-gate SOI nMOSFETs

This work analyzes the fin width dependence on induced uniaxial stress on n-type MuGFETs thought 3D simulations. A study on the stress distribution and the electric characterization of the device to measure the impact on its performance is accomplished. The stress distribution and the device performance exhibited dependence on the fin width, with higher stress transfer for narrower fins resulting in better electrical performance.

Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs

The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed, leading to the conclusion that the shift in the stress level is too small to cause a pronounced impact on the parameters. On the other hand, the reduction of the silicon fin height showed more interesting results. Despite that the standard device with smaller fin height presented a lower intrinsic voltage gain performance when compared to the reference device, when implementing strain it supersedes the reference device and presented an enhancement in the intrinsic voltage gain over the standard one up to 8 %, larger than the 5.1 % obtained for the reference device.

Fin Dimension Influence on Mechanical Stressors in Triple-Gate SOI nMOSFETs

Preliminary Data and Discussions Unstrained and strained triple-gate SOI devices under different strain techniques are studied experimentally and by simulations. As devices scale down, the fin width influence on the different strain techniques is analyzed through 3D process simulations and experimental results. The experimental devices are triple-gate SOI n-MuGFETs fabricated at imec, Belgium. The channel doping level is NA=1x10 cm, the fin height is 65nm and the gate dielectric is composed of 2.3nm HfSiON (50% Hf) on 1nm SiO2. The midgap metal gate is obtained by deposition of a 5nm TiN layer and 100nm thick polysilicon capping to complete the gate electrode. Three types of mobility boosters are applied on the devices: a strained Si layer epitaxially grown on a r-Si0.8Ge0.2 strainrelaxed buffer (SRB), an uniaxial strain obtained using the tensile strained contact etch stop layer (tCESL) technique (1), by depositing a 100nm thick nitride layer and the both methods tCESL + SiGe SRB combined. Devices have fin widths (WFin) of 20 and 870nm and a channel length (Lch) of 150nm. The structures obtained through the 3D process simulation reflect the dimensions of measured experimental devices. Fig. 1 and 2 present the simulated strain components in the vertical and longitudinal directions respectively, for the three types of strain. They are extracted vertically in the center region of the fin. The tensile strain in nMOSFETs causes, among other changes, a reduction of the bandgap, a lowering of the effective electron mass and reduces the scattering ratio of electrons, beneficial to the carrier mobility. Fig. 3 shows the maximum transconductance from experimental data (gm.max) in the upper left panel with VDS=50mV, normalized by Weff/L (where Weff=WFin+2*HFin), and in the upper right panel the gm.max enhancement due to the strain compared to unstrained devices (reference) is shown. The global electron mobility is extracted from experimental data following the Y-method (2), shown in the lower left panel, while the mobility enhancement obtained with the use of the strain with respect to the reference is shown in the lower right panel of Fig. 3. The longitudinal strain from SiGe SRB presents a uniform distribution in the channel area along the fin height with WFin=20nm having higher strain than WFin=870nm. The tCESL technique delivers a non-uniform longitudinal strain distribution along the fin height. The nonuniformity in longitudinal strain increases in the narrow fin WFin=20nm and is higher near the buried oxide interface. The combined strain returns the sum of both strains in values. However, for the normalized gm.max the tCESL returns 84.5% and 42.2% improvement over reference devices for WFin=20nm and 870nm respectively, against 58.8% and 16.2% respectively in the SiGe SRB stressor. The combined strain delivers the highest enhancement with 103.7% for WFin=20nm and 46.4% for WFin=870nm. The electron mobility delivered by reference devices, with 170.8cm/Vs and 158.8cm/Vs for WFin=20nm and 870nm respectively, lies near the range of values observed in reference (3), using similar FinFETs. The gate-to-channel electrostatic coupling and the carriers distribution for WFin=20nm may turn the global electron mobility higher in this device than for WFin=870nm, even with the larger current flowing in the top of the WFin=870nm fin due to the (100) orientation. For WFin=20nm the mobility’s behavior matches the normalized gm.max, with gains of 61.5% for SiGe SRB stressor, 84.8% for tCESL and 159.8% for the combination. However, for WFin=870nm the mobility in SiGe SRB shows only 22.7% enhancement staying at 194.9cm/Vs and the tCESL returns 369.4cm/Vs of electron mobility, resulting in 132.6% improvement. However, the electron mobility in the combined stressors decays below the tCESL values, remaining at 341.5cm/Vs with 115.1% of enhancement, a different trend from what was expected based on normalized gm.max.