Renichi Yamada

Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory

A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle

Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM

The impact of a random telegraph noise (RTN) on a scaled-down SRAM is shown for the first time. To estimate the impact on SRAM, we statistically analyzed a threshold voltage fluctuation (DeltaVth) of n-and p-MOSFETs. It is revealed that DeltaVth of the p-MOSFET is larger than that of the n-MOSFET. This difference can be explained by considering the followings: (i) number- and mobility-fluctuation models of RTN (ii) the difference in the capture cross section between electron and hole. In addition, based on these results, SRAM margin enclosed by read / write Vth curves with or without RTN was simulated. We consequently found that Vth margin comes close to Vth window of the SRAM by considering the effect of RTN on DeltaVth, even at hp 65. Moreover, DeltaVth due to RTN of the p-MOSFET is comparable with DeltaVth due to the random dopant fluctuation (RDF) at hp 45 because DeltaVth due to the RDF is inversely proportional to square root of the gate area (S), while DeltaVth due to RTN is inversely proportional to S.

Analysis of detrap current due to oxide traps to improve flash memory retention

To improve flash memory retention characteristics, we study detrap current due to oxide traps in metal-oxide-semiconductor structures (MOS capacitors and MOSFETs). We show that threshold voltage shift due to detrap current in flash memories can reach 0.6 V for 1 year. This value is detrimental for flash memory retention. Next, we analyze the two types of conduction mechanism of the detrap current, which are direct tunneling to the anode from deeper traps and thermally excited electron tunneling to the oxide conduction band from shallower traps. The deeper traps are generated by electron injection during Fowler-Nordheim stressing, while the shallower traps are generated by hole injection.

The origin of variable retention time in DRAM

To investigate the origin of DRAM variable retention time (VRT), we use test structures and carefully measure the time dependence of leakage current in DRAM. Consequently we find for the first time that the junction leakage current fluctuates just like random telegraph signal. We analyze the leakage current fluctuation in detail and find it the origin of VRT

A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memory

With the aim of improving flash-memory retention characteristics, we investigated threshold voltage shift (/spl Delta/V/sub th/) due to charge detrapping from the tunnel oxide. Accordingly, we propose a new parameter that can reveal the main origin of detrapping (hole/electron) and the detrap centroid. We found that the main origin of detrapping changes from holes to electrons depending on the degree of tunnel-oxide degradation. Since the hole detrapping increases V/sub th/ of a programmed memory cell, this V/sub th/ increase must be considered, especially when designing a multi-level flash memory.

Characterization of Charge Traps in Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) Structures for Embedded Flash Memories

A characterization of electron and hole traps in MONOS (metal-oxide-nitride-oxide-semiconductor) structures is studied to improve the reliability of embedded flash memories. Trap distributions are analyzed using a combination of avalanche charge injection and C-V (capacitance-voltage) measurement with varying thicknesses of the oxide and nitride layers in MONOS structures. We consequently find that electron traps mainly locate at both top and bottom oxide/nitride interfaces, whereas hole traps locate at the same interfaces as well as in the nitride bulk. The respective interface trap densities of the electron and hole traps are of the order of 1013 and 1012 cm-2, and the in hole trap density of the nitride bulk is of the order of 1018cm-3. We further investigate the electron trap at the oxide/nitride interface. The mechanism of electron emission from the trap is thermal assisted tunneling, and the electron trap level is distributed between 0.9 eV and 1.7 eV

Quantitative Analysis of Random Telegraph Signals as Fluctuations of Threshold Voltages in Scaled Flash Memory Cells

Random telegraph signals (RTS) in fluctuations of threshold voltage are analyzed using massive readout data in scaled flash memories. A novel quantitative analytical method is proposed to evaluate parameters of the RTS, such as amplitudes and mean time spent in individual states. This evaluation gives us a statistical view of parameters of the RTS as well as their correlations. All of the parameters were found to follow log-normal distribution and to show weak mutual dependences. Possible origins of the distributions are discussed. We also studied evolution of RTS during program/erase operations of flash memories and point out its potential similarity with breakdown phenomena in gate oxide

Characteristic Instabilities in HfAlO Metal–Insulator–Metal Capacitors Under Constant-Voltage Stress

Time-dependent characteristic changes of metal-insulator-metal (MIM) capacitors with HfAlO dielectric prepared by atomic-layer deposition under constant-voltage stress (CVS) were studied. It was found that relative dielectric constant , dielectric loss , temperature coefficient of capacitance , and frequency coefficient of capacitance gradually increase during CVS testing, whereas the voltage dependence of capacitance weakens. It was also found that changes in -value, , and during CVS testing linearly depend on changes in . These three linear relationships are basically explained by a dielectric-response model proposed for a ldquoflat-lossrdquo dielectric. That is, the increases in -value, , and are attributed to the dielectric-loss increase caused by voltage stress. Stress-time dependence of the dielectric-loss increase is expressed very well by a power function. That is, the power exponent obtained by a curve fitting linearly increases with stress voltage and decreases with increasing aluminum concentration in the HfAlO dielectric. This result indicates that aluminum addition into the HfAlO dielectric can improve the characteristic stabilities of a MIM capacitor under voltage stress.

Electron trap characteristics of silicon rich silicon nitride thin films

Charge localization causes initial retention loss and memory window narrowing after write/erase cycling in a nonvolatile memory device using a metal–oxide–nitride–oxide–semiconductor (MONOS) structure. To overcome these problems, we propose the use of silicon-rich silicon nitride (SRN) thin film as a charge-trapping layer. It was found that most of the electrons injected from the substrate were trapped at the interface between the SRN film and the top oxide and the number of electrons captured by bulk traps of the nitride is negligible. When negative bias is applied to the gate electrode, the electrons trapped at the top interface move back to the bottom interface with SRN. The high effective mobility of the electrons is presumably due to donor-like traps at 0.8 eV below the conduction band bottom of SRN.

A new method for predicting distribution of DRAM retention time

A new method for predicting the distribution of retention time of a dynamic random access memory (DRAM) by using the test element group (TEG) has been developed. The TEG is constructed of memory cells which are connected in parallel, so that the sum of memory-cell leakage currents can be measured. We verified that the t/sub ret/ main distribution can be statistically predicted from the distribution of TEG leakage current. Furthermore, we determined the measurement condition for detecting some TEGs that contain anomalously leaky cells, which limit the DRAM refreshing interval.