Riccardo Depetro

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

Abstract In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.

TCAD investigation on hot-electron injection in new-generation technologies

Abstract The hot electron injection model presently available in the TCAD tools has been investigated against experiments on new test devices to the purpose of gaining an insight on its predictability in the context of the new-generation technologies. The study has been carried out on electron emission in extremely high electric fields, as expected in power LDMOS devices at the onset of avalanche breakdown, reaching for the first time injection probabilities as high as 0.01. The numerical analysis clearly showed that the new Si/SiO2 interfaces experience different features with respect to the old ones. The TCAD method based on the deterministic solution of the Boltzmann equation can accurately capture such effects.

Hot-Carrier Degradation in Power LDMOS: Selective LOCOS- Versus STI-Based Architecture

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress.