Richard Ferrant

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework

The main goal of this paper is to study the delay evolution for future technology nodes (32 nm and beyond) using electrical circuit predictive simulations. With this aim, two SPICE predictive models, directly based on ITRS data, are developed for devices and for interconnect respectively. The predictive spice models generation is presented and validated versus 45 nm silicon data. The predictive delay evaluation is performed with buffered interconnect lines simulations. The simulation results show that the critical interconnect length should be in the order of 10 mum for the 2020 generation. Moreover, in forthcoming technologies, driver resizing and systematic buffer insertion will no longer be sufficient to systematically limit wire delay increase.

SRAM memory cell leakage reduction design techniques in 65nm low power PD-SOI CMOS

The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques change the strength of individual cell transistor, thus modifying the cell stability during the first read access following a long period of idle mode. The conclusions of the paper show that letting the bit lines float during the idle mode is mandatory to diminish the cell leakage current and help to protect the cell content against the bit-line aggressions.

1T-capacitorless bulk memory: Scalability and signal impact

The 1-transistor floating body (1TFB) memory presents a possible solution for embedded memories, as it appears to scale, and does so with standard processing. This study investigates the signal limits of 1TFB memory as technology scales. It shows that although the signal DeltaVth remains nearly constant with scaling, the memory cells become susceptible to disturbance because the amount of stored charge decreases. In addition, the transistor mismatch increases with scaling, thus limiting the ability of conventional sensing methods to correctly read the memory.