Richard G. Southwick

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Reliability challenges for the 10nm node and beyond

Technology elements for the 10nm node and beyond include FINFETs on bulk or SOI, replacement gate process, multi-workfunction gate stacks, self-aligned contacts, and alternative channel materials. This paper describes current trends and how improved physics understanding and models can enable us to anticipate the effects of scaling on reliability even in early stages of development.

SiGe composition and thickness effects on NBTI in replacement metal gate / high-κ technologies

The dependence of NBTI on SiGe thickness and composition for epitaxially grown layers on (100) and (110) Si substrates is studied in detail. It is found that SiGe thickness has no significant impact on NBTI at lower Ge%. However, lower NBTI degradation was observed with increasing Ge%, even though the interface state densities (Nit) increase with respect to Si. This improved NBTI is due to band offset limited VT, indicating that the improvement is substrate related rather than interface related. The physical mechanism is then discussed in terms of Ge%-induced variation in the band alignment.

SOI FinFET versus bulk FinFET for 10nm and below

FinFETs may in principle be built on either bulk [1-3] or SOI [4-5] substrates. In this paper we will review some of the technical issues associated with choice of substrate, directly comparing empirical results on 10nm hardware for which all the other processes are as much the same as possible. Furthermore, we will discuss the challenges beyond the 10nm generation, where fundamental changes in materials may render the debate moot. Our conclusion and prognosis is that SOI was, is, and will continue to be the technically superior choice.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

Reliability monitoring for highly leaky devices

We demonstrate a new charge pumping (CP) methodology, frequency modulated CP (FMCP), that robustly treats metrology challenges associated with high gate leakage current. By moving to an AC coupled measurement, we are able to easily resolve small CP signals despite excessively high gate leakage current backgrounds. We demonstrate the utility of FMCP as a reliability monitoring tool in highly scaled and highly leaky devices.

Process optimizations for NBTI/PBTI for future replacement metal gate technologies

Bias Temperature Instability (BTI) is a tremendous reliability concern for deeply scaled CMOS technologies, and is the limiting mechanism for further inversion layer thickness (Tinv) scaling for future nodes [1]. Replacement Metal Gate technologies are of particular concern, since the gate stack is not exposed to the high temperature source/drain anneals. We have identified four strategies for reducing BTI in Replacement metal gate technologies: Rapid Thermal Anneal (RTA) optimization, optimization of the HfO2 layer thickness, introducing a gate dielectric dopant for NBTI reduction, and effective Work Function tuning. Judiciously combining these four techniques enable further Tinv scaling for 10 nm and below.

Total Ionizing Dose Radiation Effects on 14 nm FinFET and SOI UTBB Technologies

14 nm technology node bulk silicon FinFETs and SOI FinFETs and 14 nm SOI Ultra-Thin-Body and BOX nFETs were irradiated under bias using a 10 keV X-ray source. Irradiation resulted in significant changes in the threshold voltages of the SOI devices and large changes in the off-state current of the bulk FinFETs.

Frequency-Modulated Charge Pumping With Extremely High Gate Leakage

Charge pumping (CP) has proved itself to be one of the most utilitarian methods to quantify defects in MOS devices. In the presence of low-to-moderate gate leakage, CP quantification is most often implemented via a series of measurements at multiple frequencies. However, this approach is ill-equipped to handle excessive leakage currents common in advanced technologies. In this paper, we transform multifrequency CP from a quasi-dc measurement into a true ac measurement. This ac detection scheme, called frequency-modulated CP, is far better equipped to deal with high levels of leakage currents and thereby extends the usefulness of CP to current and future device technologies where excessive leakage is the norm. Additionally, we show that multifrequency CP has a long overlooked error that becomes significant in high-leakage situations. We discuss the origins of this error in detail and outline mitigation methodologies. Finally, we explore timing and voltage limitations of waveform generators and how these experimental boundary conditions impact on both frequency-dependent and FMCP.

Frequency-Modulated Charge Pumping: Defect Measurements With High Gate Leakage

Charge pumping is one of the most relied techniques used to quantify interface defects in metal-oxide-semiconductor devices. However, conventional charge pumping is easily hindered by excessive gate leakage currents, which render the technique unsuitable for advanced technology nodes. We demonstrate a new frequency-modulated charge pumping methodology in which we transform the quasi-dc charge pumping measurement into an ac measurement. The ac detection scheme is highly resistant to gate leakage currents and extends the usefulness of charge pumping as a defect monitoring tool for future technologies.