Miaomiao Wang

Reliability of advanced high-k/metal-gate n-FET devices

Hot-carrier degradation and bias-temperature instability of FinFET and fully-depleted SOI devices with high-k gate dielectrics and metal gates are investigated. Thinner SOI results in increased hot-carrier degradation, which can be recovered by junction engineering. FinFETs with (1 1 0) Si active surfaces exhibit degradation of sub-threshold swing after hot carrier stress, indicating generation of interface states. The effect of duty cycle on bias-temperature instability modulates the quasi-steady-state trap occupancy over a broad distribution of electron trapping and de-trapping times. Only the deeper traps remain filled for low duty cycle, and shallower traps are emptied during AC stress.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

We report FDSOI devices with a 20nm gate length (L_G) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V_dd of 0.75V, competitive effective current (I_eff) reaches 550/340 μA/μm for NFET, at I_off of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V_dd of 0.75V, PFET I_eff reaches 495/260 μA/μm, at I_off of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.

Reliability challenges for the 10nm node and beyond

Technology elements for the 10nm node and beyond include FINFETs on bulk or SOI, replacement gate process, multi-workfunction gate stacks, self-aligned contacts, and alternative channel materials. This paper describes current trends and how improved physics understanding and models can enable us to anticipate the effects of scaling on reliability even in early stages of development.

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

A significant increase in parasitic resistance (R<inf>PARA</inf>) fluctuation is observed when S/D length is getting smaller than the characteristic length (L<inf>TRANS</inf>). Resistance change evaluated on double gate finFETs with various fin lengths shows an excellent agreement between the experimental data and the analytical model. Further R<inf>PARA</inf> fluctuation improvement can be realized by optimizing the L<inf>TRANS</inf>.

Process optimizations for NBTI/PBTI for future replacement metal gate technologies

Bias Temperature Instability (BTI) is a tremendous reliability concern for deeply scaled CMOS technologies, and is the limiting mechanism for further inversion layer thickness (Tinv) scaling for future nodes [1]. Replacement Metal Gate technologies are of particular concern, since the gate stack is not exposed to the high temperature source/drain anneals. We have identified four strategies for reducing BTI in Replacement metal gate technologies: Rapid Thermal Anneal (RTA) optimization, optimization of the HfO2 layer thickness, introducing a gate dielectric dopant for NBTI reduction, and effective Work Function tuning. Judiciously combining these four techniques enable further Tinv scaling for 10 nm and below.

Copper Contact for 22 nm and Beyond: Device Performance and Reliability Evaluation

We demonstrate the device performance benefit of Cu contact over W contact using high-κ/metal gate CMOS devices. The ring oscillator (RO) device of Cu contact showed reduction in external resistance, which resulted in an increase in drive current by 5% for both nFET and pFET devices. The delay on the gate-cap-loaded RO improved by 5%-7% with Cu contact. We evaluated device reliability tests for gate dielectric breakdown, positive-bias temperature instability, negative-bias temperature instability, and hot carrier injection on 32- and 22-nm-node devices with Cu contact. The reliability results for the Cu contacts with the reliable barrier layer and good gap fill are comparable to those of W contacts.

Air spacer for 10nm FinFET CMOS and beyond

For the first time, we report integration of air spacers with FinFET technology at 10nm node dimensions. The benefit of parasitic capacitance reduction by air spacers has been successfully demonstrated both at transistor level (15–25% reduction in overlap capacitance (COT)) and at ring oscillator level (10–15% reduction in effective capacitance (Cf)). Key process challenges and device implications of integrating air spacers in FinFET are identified. We propose a partial air spacer scheme, in which air spacers are formed only above fin top and sandwiched by two dielectric liners, as a viable option to adopt air spacers in FinFET technology with minimal risks to yield and reliability.

HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS

Hot-carrier degradation (HCI) in aggressively scaled undoped-body devices is carefully studied and compared for high-k/metal gate FINFETs and extremely thin silicon-on-insulator (ETSOI) transistors. We show that HCI involves different degradation mechanisms for silicon-on-insulator (SOI)-FINFETs and ETSOI devices though both are fabricated on undoped body. For FINFETs, the HC degradation correlated with interface trap generation in the channel region, whereas for ETSOI, trap generation and electron trapping in the spacer-nitride region were observed.

Comparison of DC and AC NBTI kinetics in RMG Si and SiGe p-FinFETs

An ultrafast characterization method is used to study DC and AC NBTI in Si and SiGe channel core RMG p-FinFETs. The time evolution of degradation during and after stress, and the impact of stress bias, temperature, frequency and duty cycle are characterized. A physics-based model is used to qualitatively explain measured data. The similarities and differences of DC and AC NBTI in Si and SiGe channel devices are highlighted.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.