James H. Stathis

Percolation models for gate oxide breakdown

Computer calculations of the formation of a percolation path across a finite lattice are used to model dielectric breakdown. The classical scaling relations for percolation are expected to be valid only for large (finite) systems near pc. We investigate the opposite limit of very small samples, comparable to the lattice spacing. It is shown that relatively simple numerical calculations can quantitatively describe the statistics and thickness dependence of oxide breakdown in thin samples. The critical defect density for breakdown shows a strong decrease with thickness below about 5 nm, then becomes constant below 3 nm. Both of these features can be quantitatively explained by percolation on a finite lattice. The effective defect “size” of about 3 nm is obtained from the thickness dependence of the breakdown distributions. The model predicts a singular behavior when the oxide thickness becomes less than the defect size, because in this limit a single defect near the center of the oxide is sufficient to crea...

Luminescence degradation in porous silicon

We have studied the stability of the luminescence from porous Si in the presence of a variety of ambient gases (e.g., N2, H2, forming gas, and O2). Although the optical properties are fairly stable under most conditions, illumination in the presence of O2 causes a substantial decrease in luminescence efficiency. Infrared measurements show that the surfaces of degraded samples are oxidized. The luminescence lifetime of the degraded material is found to be substantially reduced, and the density of Si dangling bonds increases by more than two orders of magnitude, which suggests that oxidation of the surface introduces nonradiative recombination channels. These observations indicate that the electronic properties at the surface of the porous Si play a key role in obtaining efficient luminescence from this material.

The negative bias temperature instability in MOS devices : a review

Abstract Negative bias temperature instability (NBTI), in which interface traps and positive oxide charge are generated in metal–oxide–silicon (MOS) structures under negative gate bias, in particular at elevated temperature, has come to the forefront of critical reliability phenomena in advanced CMOS technology. The purpose of this review is to bring together much of the latest experimental information and recent developments in theoretical understanding of NBTI. The review includes comprehensive summaries of the basic phenomenology, including time- and frequency-dependent effects (relaxation), and process dependences; theory, including drift–diffusion models and microscopic models for interface states and fixed charge, and the role of nitrogen; and the practical implications for circuit performance and new gate-stack materials. Some open questions are highlighted.

Dielectric breakdown mechanisms in gate oxides

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

Passivation and depassivation of silicon dangling bonds at the Si/SiO2 interface by atomic hydrogen

Atomic hydrogen is found to simultaneously passivate and depassivate silicon dangling bonds at the Si(111)/SiO2 interface at room temperature via the reactions Pb+H0→PbH and PbH+H0→Pb+H2. The passivation reaction occurs more efficiently keeping the steady‐state Pb density at a low value of only 3–6×1011 cm−2 during atomic hydrogen exposure. This low Pb density can only account for a small fraction of the total number of interface states produced by atomic hydrogen.

Reliability projection for ultra-thin oxides at low voltage

The rate of defect generation by electrical stress in silicon dioxide has been measured as a function of gate voltage down to 2 V on a variety of MOSFETs with thickness in the range 1.4-5 nm. The critical defect density necessary for destructive breakdown has also been measured in this thickness range. These quantities are used to predict time to breakdown for ultra thin oxides at low voltages. The properties of the breakdown distribution, which becomes broader as the oxide thickness is reduced, are used to provide reliability projections for the total gate area on a chip. It is predicted that oxide reliability may limit oxide scaling to about 2.6 nm (CV extrapolated thickness) or 2.2 nm (QM thickness) for a 1 V supply voltage at room temperature and that the current SIA roadmap will be unattainable for reliability reasons by sometime early next century.

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 mm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown, Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

Hybrid-orientation technology (HOT): opportunities and challenges

At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Threshold voltage (V_t) of a field effect transistor (FET) is observed to shift with stressing time and this stress induced V _t shift is an important transistor reliability issue. V_t shifts that occur under negative gate bias is referred as NBTI and those that occur under positive bias is referred as PBTI or charge trapping. In this paper, we present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials. The study has two parts. In part I, NBTI and PBTI measurements are performed for FUSI NiSi gated FETs with SiO₂ SiO₂/HfO₂ and SiO₂/HfSiO as gate dielectric stacks and the results are compared with those for conventional SiON/poly-Si FETs. The main results are: (i) NBTI for SiO ₂/NiSi and SiO₂/HfO₂/NiSi are same as those conventional SiON/poly-Si FETs; (ii) PBTI significantly increases as the Hf content in the high K layer is increased; and (iii) PBTI is a greater reliability issue than NBTI for HfO₂/NiSi FETs. In part II of the study, NBTI and PBTI measurements are performed for SiO2/HfO2 devices with TiN and Re as gates and the results are compared with those for NiSi gated FETs. The main results are: (i) NBTI for SiO ₂/HfO₂/TiN and SiO₂/HfO₂/Re pFETs are similar with those observed for NiSi gated pFETs; and (ii) PBTI in TiN and Re gated HfO₂ devices is much smaller than those observed for SiO₂/HfO₂/NiSi. In summary for SiO₂/HfO₂ stacks, NBTI is observed to be independent of gate material whereas PBTI is significantly worse for FUSI gated devices. Consequently, HfO₂ FETs with TiN and Re gates exhibit over all superior transistor reliability characteristics in comparison to HfO₂/FUSI FETs

Ultra-thin oxide reliability for ULSI applications

In this article, we critically examine the limit of gate oxide scaling from a reliability point of view. The thickness dependence of the characteristic breakdown time (charge) and Weibull slope as well as the temperature dependence of oxide breakdown are measured with emphasis on accuracy. The failure modes of soft and hard breakdown events and their impact on device characteristics are reviewed. Using a two-dimensional reliability analysis, we explore the relative importance of characteristic breakdown time and Weibull slope in lifetime projection, and the possibilities of extending gate oxide beyond the currently predicted limit.