Kunal R. Parekh

Metal Gate Recessed Access Device (RAD) for DRAM Scaling

A functional DRAM with higher data retention characteristics than a planar access device has been demonstrated, using a metal gate recessed access device (RAD). Chemical vapor deposition (CVD) and atomic layer deposition (ALD) were used to deposit titanium nitride (TiN) and tantalum nitride (TaN), respectively. CVD TiN and ALD TaN-CVD TiN laminate gate stacks were integrated with a RAD module. ALD TaN-CVD TiN laminate gates showed enhanced drive current (IDS), higher transconductance (GM), higher mobility (¿EFF) and reduced off current (IOFF) characteristics compared to CVD TiN gates. Device characteristics and reliability data for both the planar devices and RADs are presented. The ALD TaN-CVD TiN laminate metal gate RAD showed much improved data retention characteristics compared to a conventional planar device with a poly silicon gate. The optimum thickness of ALD TaN in the laminate stack is discussed.

Small-Signal Analysis and Modeling of Asymmetric Source/Drain Parasitic Resistances for DRAM Access Transistors in Low-Power Applications

The small-signal conductance technique was extended to extract asymmetric source/drain parasitic resistances. It was also applied in order to analyze the tWR delay of DRAM cell transistors in production and to develop a non-planar cell transistor such as recessed access device (RAD) for low-power DRAM cells. Factors limiting the drive current for planar and non-planar access transistors in the low-power DRAM cells were discussed

Time-dependent dielectric breakdown of a recessed channel DRAM access device

A recessed access device (RAD) used in a DRAM cell has exhibited advantages over the conventional planar access device, including retention time improvement. However, worse time-dependent dielectric breakdown (TDDB) characteristics were observed for RAD. The degraded TDDB performance is primarily attributed to thinner oxide growth in the recess