Mark D. Jaffe

CMOS Imager with Copper Wiring and Lightpipe

A CMOS imager technology is described, which uses Cu wiring and a polymer lightpipe. The microlens height must be optimized when using the lightpipe, so that light is focused into the top of the lightpipe rather than onto the photodiode. A SiN layer is used on the sidewalls to reflect light that enters the top of the lightpipe down onto the photodiode. The SiN layer also forms a hermetic seal, which protects the Cu wiring from ambient moisture. Using this structure, high quantum efficiency can be achieved for a 2.2 mum pixel and high reliability is demonstrated

Power handling capability of an SOI RF switch

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

Lateral tapered active field-plate LDMOS device for 20V application in thin-film SOI

We present a new device design for 20V application in thin body SOI technology. High breakdown voltage is achieved by forming RX-bound field plates which deplete the drift region of an LDMOS structure using only lateral electric field coupling. A baseline 180nm CMOS SOI process is utilized and RX field plate shapes are designed to result in an essentially uniform longitudinal drift region electric field satisfying the RESURF principal. We studied device scaling and the effect of varying the width and length of the angular RX field plates and their relation to impact ionization rate in both floating body and body-contacted n-channel LDMOS deices. 3D TCAD simulations were used to investigate the effect design parameters on electric field and impact ionization. Unitary 20V rated-LDMOS devices are experimentally demonstrated, verifying a LDMOS option to stacked CMOS for high voltage applications in SOI technology.

A high-resistivity SiGe BiCMOS technology for WiFi RF front-end-IC solutions

We present for the first time a novel high resistivity bulk SiGe BiCMOS technology that has been optimized for a WiFi RF front-end-IC (FEIC) integration. A nominally 1000 Ohm-cm p-type silicon substrate is utilized to integrate several SiGe HBTs for power amplifiers (PAs), a SiGe HBT low-noise amplifier (LNA), and isolated nFET RF switch device. Process elements include trench isolation for low-loss passives and reduced parasitic coupling, and a lower-resistivity region for the FETs to minimize changes to the circuit library.

Improvements in SOI technology for RF switches

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.

High-resistivity SiGe BiCMOS technology development

IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS technology in 2011. This technology was optimized for WiFi and cellular NPN power amplifier (PA), NPN low noise amplifier (LNA), and isolated CMOS NFET switch rf front-end-IC (FEIC) integration. It includes an optional through silicon via used as a low inductance ground path for NPN emitters. Data for 50 Ω-cm, 1st generation HiRES, and 2nd generation HiRES NPN PA, LNA, and CMOS NFET switch devices are reviewed.

Reliability of circuits under pads for Au and Cu wire bonding

The reliability of circuits (wiring and vias) under bond pads has been studied for both Au wire bonding and Cu wire bonding, for bond pads and wiring levels typical of those used in RF technology. Electrical test structures under bond pads were used to characterize wire and via integrity after wire bonding and reliability stresses. In addition, SEM analysis was used to inspect for possible damage to the structures under bond pads after wire bonding. No damage was observed with either electrical testing or with SEM analysis, indicating that it is possible to allow a large variety of layouts under bond pads for both Au wire bonding and Cu wire bonding.

Reliability of segmented edge seal ring for RF devices

RF devices are sensitive to noise coupling between devices. One source of coupling is the edge seal ring. We propose using a segmented guard ring to reduce coupling between devices. We demonstrate that the segmented guard ring is reliable for a 0.18 μm RF technology.

Stitched large format CMOS image sensors for dental x-ray digital radiography

In this paper, we present a family of large format CIS’s designed for dental x-ray applications. The CIS areas vary from small 31.5mm x 20.1mm, to medium 34.1mm x 26.3mm, to large 37.1mm x 26.3mm. Pixel size is 19.5um x 19.5um. The sensor family was fabricated in a 0.18um CIS process. Stitching is used in the CIS fabrication for the medium and large size sensors. We present the CIS and detector system design that includes pixel circuitry, readout circuitry, x-ray trigger mechanism, scintillator, and the camera electronics. We also present characterization results including the detector performances under both visible light and x-ray radiation.

Interconnect and Packaging Technology for CMOS Image Sensors (Invited)

2. Basis Operation The CMOS imager consists of an array of pixels that detect the incident light. A commonly used pixel is the four transistor or “4T” cell (Fig. 1) [2]. To capture an image, the photodiode is first reversed biased (set to Vdd) using the reset gate and transfer gate (Fig. 2). When the shutter of the camera is opened, light that is incident on the photodiode will generate electron-hole pairs. To sense the charge in the photodiode, the transfer gate is turned on and the charge is moved to the floating diffusion. This changes the potential on the gate of the the source-follower circuit, and the resulting signal is detected at the output of the pixel by turning on the row select transistor. The photo-diode area is much smaller than the total area of the pixel. To overcome this loss of sensitivity, microlenses are used to focus light on the photo-diodes [3]. The quantum efficiency (i.e., the percentage of photogenerated carriers that are detected for each incoming photon) is greatly improved by using microlenses . In order to capture color information from the broad bandwidth incident light, color filters are used so that each pixel captures mainly one color of light (i.e., red, green, or blue). The color filters consist of dyed photoresist that is arranged in alternating rows or either green and blue or green and red [4]..