John J. Ellis-Monaghan

A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBMs large volume 200mm fabrication line. The technology features 300 GHz fT and 360 GHz fMAX high performance SiGe HBTs, 135 GHz fT and 2.5V BVCEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

Demonstration of a High Extinction Ratio Monolithic CMOS Integrated Nanophotonic Transmitter and 16 Gb/s Optical Link

We present a 16-Gb/s transmitter composed of a stacked voltage-mode CMOS driver and periodic-loaded reverse biased pn junction Mach-Zehnder modulator. The transmitter shows 9-dB extinction ratio and 10.3-pJ/bit power consumption and operates with 1.3 μm light. Penalties as low as 0.5 dB were seen as compared to a 25-Gb/s LiNbO3 transmitter with both a monolithic metal-semiconductor-metal receiver and a reference receiver at 16-Gb/s operation. We also present an analytic expression for relative transmitter penalty (RTP), which allows one to quickly assess the system impact of design parameters such as peak-to-peak modulator drive voltage, modulator figure of merit, and transmitter extinction ratio to determine the circumstances under which a stacked CMOS cascode driver is desirable.

CMOS Imager with Copper Wiring and Lightpipe

A CMOS imager technology is described, which uses Cu wiring and a polymer lightpipe. The microlens height must be optimized when using the lightpipe, so that light is focused into the top of the lightpipe rather than onto the photodiode. A SiN layer is used on the sidewalls to reflect light that enters the top of the lightpipe down onto the photodiode. The SiN layer also forms a hermetic seal, which protects the Cu wiring from ambient moisture. Using this structure, high quantum efficiency can be achieved for a 2.2 mum pixel and high reliability is demonstrated

Demonstration of Error-Free 32-Gb/s Operation From Monolithic CMOS Nanophotonic Transmitters

We present a monolithic CMOS-integrated nanophotonic transmitter with a link sensitivity comparable with a 25-Gb/s commercial reference transmitter. Our CMOS transmitter shows error-free operation up to 32 Gb/s, and exhibits a 4.8-dB extinction ratio and 4.9-dB insertion loss at 25 Gb/s.

An integrated silicon photonics technology for O-band datacom

A manufacturable platform of CMOS, RF and opto-electronic devices fully PDK enabled to demonstrate a 4×25 Gb/s reference design is presented. With self-aligned fiber attach, this technology enables low-cost O-band data-com transceivers. In addition, this technology can offer enhanced performance and yield in hybrid-assembly for applications at 25 Gbaud and beyond.

Monolithic Travelling-Wave Mach-Zehnder Transmitter with High-Swing Stacked CMOS Driver

We present a 20 Gb/s monolithically integrated transmitter with stacked CMOS driver and periodic-loaded PN-junction Mach-Zehnder modulator fabricated in IBMs sub-100nm technology node. Transmitter extinction ratios of 10 dB at 20 Gb/s are demonstrated.

Power handling capability of an SOI RF switch

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

Improvements in SOI technology for RF switches

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.

A linear push-pull silicon optical modulator

We present a linear push-pull driven silicon modulator fabricated in IBM’s CMOS9WG technology node. The Si modulator shows third order nonlinearity suppression 3 dB superior in comparison with a commercial lithium niobate modulator.