Richard S. Wise

(Ba,Sr)TiO 3 dielectrics for future stacked- capacitor DRAM

Thin films of barium-strontium titanate (Ba,Sr)TiO3 (BSTO) have been investigated for use as a capacitor dielectric for future generations of dynamic random-access memory (DRAM). This paper describes progress made in the preparation of BSTO films by liquid-source metal-organic chemical vapor deposition (LS-MOCVD) and the issues related to integrating films of BSTO into a DRAM capacitor. Films of BSTO deposited on planar Pt electrodes meet the electrical requirements needed for future DRAM. The specific capacitance and charge loss are found to be strongly dependent on the details of the BSTO deposition, the choice of the lower electrode structure, the microstructure of the BSTO, the post-electrode thermal treatments, BSTO dopants, and thin-film stress. Films of BSTO deposited on patterned Pt electrodes with a feature size of 0.2 µm are found to have degraded properties compared to films on large planar structures, but functional bits have been achieved on a DRAM test site at 0.20-µm ground rules. Mechanisms influencing specific capacitance and charge loss of BSTO films are described, as are the requirements for the electrode and barrier materials used in stacked-capacitor structures, with emphasis given to the properties of the Pt/TaSi(N) electrode/barrier system. Major problems requiring additional investigation are outlined.

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.

Plasma-etching processes for ULSI semiconductor circuits

An overview is presented of plasma-etching processes used in the fabrication of ULSI (ultralarge-scale integrated) semiconductor circuits, with emphasis on work in our facilities. Such circuits contain structures having minimum pattern widths of 0.25 µm and less. Challenges in plasma etching in evolving to such dimensions have come from the implementation of antireflective coatings and thinner, more etchsensitive photoresists; the increased aspect ratios needed to meet design requirements; the additional hard-mask etching steps needed at levels at which lithography is unsuitable for patterning; and increased selectivity requirements, such as the requirement that contact structures be self-aligning. Future circuit density and performance requirements dictate tighter specifications for linewidth variations permitted across a wafer, microloading effects, and device damage. As a result, plasma-etching systems for critical levels are migrating from traditional multifilm, capacitively coupled low-density-plasma systems to medium- and high-density-plasma systems employing exotic or highly polymerizing chemical species specifically designed for one type of film.

Hardmask technology for sub-100-nm lithographic imaging

The importance of hardmask technology is becoming increasingly evident as the demand for high-resolution imaging dictates the use of ever-thinner resist films. An appropriately designed etch resistant hardmask used in conjunction with a thin resist can provide the combined lithographic and etch performance needed for sub-100 nm device fabrication. We have developed a silicon-based, plasma-enhanced chemical vapor deposition (PECVD) prepared material that performs both as an antireflective coating (ARC) and a hardmask and thus enables the use of thin resists for device fabrication. This ARC/hardmask material offers several advantages over organic bottom antireflective coatings (BARC). These benefits include excellent tunability of the materials optical properties, which allows superior substrate reflectivity control, and high etch selectivity to resist, exceeding 2:1. In addition, this material can serve as an effective hardmask etch barrier during the plasma etching of dielectric stacks, as the underlying silicon oxide etches eight times faster than this material in typical fluorocarbon plasma. These properties enable the pattering of features in 1-2 μm dielectric stacks using thin resists, imaging that would otherwise be impossible with conventional processing. Potential extendibility of this approach to feature sizes below 100nm has been also evaluated. High resolution images as small as 50nm, have been transferred into a 300nm thick SiO2 layer by using Si ARC/hardmask material as an etch mask. Lithographic performance and etch characteristics of a thin resist process over both single layer and index-graded ARC/hardmask materials will be shown.

Integrated non-SO2 underlayer and improved line-edge-roughness dielectric etch process using 193nm bilayer resist

We present an integrated reactive ion etch (RIE) process using bilayer (a top imaging layer and a bottom underlayer) thin film imaging system to push the limits of 193nm wavelength photolithography. Minimizing the line-edge roughness (LER) and maintaining the critical dimension (CD) of the transferred pattern are important in high-resolution RIE. Along with LER and CD issues and shrinking ground rules, deleterious effects of SO2 in the underlayer etch chemistry necessitated the development of non-SO2 chemistry. Thus a N2–H2–CO chemistry was developed and integrated with the etch process of underlying borophosphosilicate glass using Ar–O2–C4F8–CO–CH3F chemistry.

Tunable antireflective coatings with built-in hard mask properties facilitating thin-resist processing

Patterning sub-150 nm features in dielectric stacks using single layer resist processes in conjunction with organic anti-reflective coatings (ARCs) is becoming very difficult. Typical organic ARC-open etch processes suffer from poor ARC-to-resist selectivities (~0.7), and are accompanied by critical dimension (CD) losses. The resist remaining is often not sufficient to prevent artifacts such as substrate microrevicing during subsequent etches. PECVD-Deposited titanium nitride and silicon oxynitride films have been investigated as ARC layers but their basic nature has caused residue formation at the resist/ARC interface. We have developed a PECVD-deposited material, TERA (Tunable Etch-Resistant ARC) that acts as an ARC at 248 nm and 193 nm wavelengths and provides excellent etch selectivity to resist surpassing those attained with organic ARCs. In addition, this material demonstrates excellent hard mask properties for subsequent dielectric etch steps. The optical properties of these films can be easily tuned to minimize substrate reflectance at either imaging wavelength by controlling the precursor composition and deposition conditions. The films are compatible with 248 nm and 193 nm resists - no footing, undercut or residue is observed during patterning. The films can be etched selectively to resist (selectivity ~2.5) that translates to less resist consumption during th ARC-open etch. Compared to resists, TERA demonstrates better etch resistance while patterning dielectric stacks - the silicon oxide-to-TERA Selectivity exceeds 8. In this paper, the excellent optical tunability and substrate reflectivity control achieved with TERA are discussed. Clean lithography using 248 nm, 193 nm and e- beam resists is shown. The etch characteristics of TERA in fluorocarbon and halogen-based plasma chemistries are discussed. Finally, the formation of 135 nm and 120 nm deep trench patterns in thick dielectric stacks using TERA in conjunction with commercial 248 nm and 193 nm resists, respectively is demonstrated. The extendability of this approach to pattern silicon without roughening or microrevicing using sub-200 nm thick resists is motivated.

Controlling line-edge roughness and reactive ion etch lag in sub-150 nm features in borophosphosilicate glass

We have developed a reactive ion etch (RIE) process in borophosphosilicate glass (BPSG) for 150 nm line-and-space features, where line-edge roughness (LER) complemented with RIE lag becomes a major issue. Effect of flow rates and carbon-to-fluorine atomic ratio of fluorohydrocarbon gases was utilized to achieve acceptable process window allowing lower radio frequency powers therefore obtaining acceptable LER and RIE lag in the high-resolution features etched into BPSG.

Etching silicon-containing bilayer resists in ammonia-based plasmas

The need to print smaller feature sizes has led to the shift from 248nmto193nm lithography. The disadvantages of 193nm ArF single-layer resist materials, such as lower depth of focus and lower etch resistance, have made thin-film imaging (TFI) techniques an attractive alternative. In the bilayer (comprised of an image layer and an underlayer) approach, a form of TFI, O2-based plasma chemistries are used for the transfer etches whereby oxidation of silicon in the image layer provides the required etch resistance. However, use of oxygen results in profile and critical dimension (CD) control issues. While gas additives have helped minimize these problems, there are other accompanying disadvantages. In this work, the feasibility of a non-O2-containing NH3-based plasma etch chemistry was evaluated. Effects of additive gases, such as N2, H2, and C2H4, were investigated. Surface analysis of the resist showed that nitrogen from the gas phase was incorporated in the surface of the image layer during the etch, and ...