Bomy A. Chen

0.18 um modular triple self-aligned embedded split-gate flash memory

A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.

Scalability and biasing strategy for CMOS with active well bias

We analyze the scalability of the two well bias strategies: reverse bias to reduce standby power, and forward bias to improve the speed or to reduce active power. We then present the device design space that includes well bias as an integral part of the design variables following the SIA Roadmap specifications. We show that proper well biases are needed for bulk CMOS just to continue to meet the SIA Roadmap requirements for performance and standby current. The scalabilities for forward bias and reverse bias are different. The advantage of reverse bias is diminishing with scaling due to low initial V/sub t/ values, short-channel effects, and band-to-band tunneling. The advantage of the forward body bias is preserved better with scaling due to high initial V/sub t/ values as well as smaller depletion width, and increases with V/sub t/ nonscaling. The forward bias approach is not effective in speed improvement for ultra-high performance applications with high V/sub dd/ overdrive and low V/sub t/ to start with, but is effective in active power reduction at a fixed speed target.

A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications

A leading-edge 0.13 /spl mu/m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 nm lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 /spl mu/m/sup 2/ functional 6T-SRAM cell is demonstrated.

Yield improvement for a 3.5-ns BiCMOS technology in a 200-mm manufacturing line

Various issues pertinent to producing high volumes of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The technology consists of a baseline 0.8- mu m CMOS process with four levels of metal and 0.45- mu m L/sub eff/ FETs, to which has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with As-doped polysilicon, and an antimony-doped subcollector. Chips fabricated in the technology include a 3.5-ns 576 K BiCMOS SRAM and a 200 K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, a spurious polysilicon filament, management of the critical emitter window image, and modulation of the titanium silicide/silicon interfacial resistance are considered.<<ETX>>

Silicon on insulator-an emerging high-leverage technology

Silicon on insulator (SOI) has emerged as a high-leverage technology for a wide range of commercial and military applications. While the use of SOI is presently limited to special niche applications, such as radiation-hard space and defense electronics, thin-film SOI has become strategic for low-power, battery-operated portable systems and large-scale integrated logic and memory circuits with sub-half micron features. Substantial process simplification and cost reduction result from the dielectrically isolated structures. Other important SOI applications are the merger of several functions on the same die that performs reliably in adverse high-temperature environments. These include analog and logic functions, smart micromechanical sensors for automotive and distributed jet engine control with logic functions, or smart high-voltage CMOS logic/control elements. Manufacturable solutions to several material and device problems, however, must be demonstrated before SOI CMOS or BiCMOS designs enter the high-volume commercial manufacturing stage. Among these are the availability, cost, and quality of SOI material, gettering, electrostatic discharge protection, the floating-body problem in thin-film structures, and self-heating effects caused by the low thermal conductivity of the buried-oxide layer. The status of SOI material is discussed, including the different methods used to prepare large SOI wafers, wafer availability, cost reduction strategies, material characterization, and material quality. Applications and leverage areas are also described, with emphasis on problems and challenges that lie ahead for the large-scale manufacture of SOI products. The potential economic impact of SOI technology on the profitability of semiconductor manufacturing is described. >

Optimization of a High-Volume 200-mm BiCMOS Manufacturing Line

Terence Hook, Bomy Chen, Gorden Starkey, Arup Bhattacharyya, Margaret Faucher, Carol Racine, Christa Willets, Steven Eslinger, Subhash Kulkarni, William King, Carol Washburn, Joseph Piccirillo, Steven Mongeon, Arthur Johnson, Edward Gabrielle IBM Technology Products Essex Junction, VT 05452, USA Several issues relevant to yield improvement in a highvolume production of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The baseline technology is a 0.8-pm CMOS process with four levels of metal and 0.45-pm Le, FETs. To this has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with an As-doped polysilicon emitter, and an antimonydoped subcollector. Products fabricated in the technology include a 3.5-ns 576K BiCMOS SRAM and a 200K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, bipolar beta control, an oxide pinhole defect, and control of the titanium silicide sheet resistance are considered.

Key issues for the unplanned transfer of VLSI technology

The authors point out that in unplanned transfers i.e. capacity overload of technology license, etc., many manufacturing issues must be resolved on an aggressive schedule and at the lowest possible cost. The key issues which exist under various conditions are covered. The balance between technology requirements and minimized impact is discussed in terms of processing tools and recipes. Critical issues are identified and potential solutions discussed. A working model for unexpected semiconductor technology transfer tasks is presented. The methodology used to meet constrained budgets and aggressive schedules are the basic assumption for the proposed model.<<ETX>>