Rick C. Jerome

Advanced single poly BiCMOS technology for high performance programmable TTL/ECL applications

An optimized process has been developed by integration of several high-performance device modules such as PtSi Schottky barrier diodes, lateral p-n-p transistors, and electrically programmable fuse elements into the 0.6- mu m L/sub eff/ high-performance advanced BiCMOS (ABiC IV) process. Due to unique device/process requirements for each module, a process flow has been designed to completely decouple the individual modules from each other to prevent process marginalities and tradeoffs. This technology is especially attractive for high-performance and high-density BiCMOS TTL/ECL (transistor transistor logic/emitter coupled logic) applications requiring electrically programmable fuse elements.<<ETX>>

1.5 nsec ECL-PAL realization using advanced single poly technology

The second generation of the advanced single poly emitter coupled technology (ASPECT-II) has been tailored to fabricate an emitter-coupled-logic (ECL) programmable array logic (PAL) product with maximum specified propagation delay of 2 ns. The device is designed as a programmable AND array driving a fixed OR array and is organized as 16 complementary output functions. Complementary outputs eliminate the need for external inverters and also provide signals that can be used in differential interconnect for situations requiring increased noise immunity. All input pins have on-chip 50- Omega pull-down resistors. A maximum propagation delay of 2 ns at a power dissipation of 1.2 W has been achieved. The logic path of this component has been minimized to three ECL gates in order to achieve the required performance. The product is available in both industry standard ECL 100 K and 10 KH logic families.<<ETX>>

Application of lightly doped buried-layer for the reduction of the interconnection and junction capacitances

Interconnection delay plays a dominant role in determining the speed performance of todays integrated circuits. It is shown that the formation of a lightly doped buried layer (LDBL) reduces the capacitance of wiring leads and bonding pads with respect to the substrate. LDBL also improves the collector-to-substrate capacitance of npn transistors as well as the tub-to-substrate capacitance of MOS transistors. As a result the speed performance of the products employing this technique is significantly improved. Because of the relative simplicity of the process, the ratio of percent delay reduction to percent cost increase is expected to be smaller than for any alternative approach.<<ETX>>