Madan Biswal

0.6 amu;m, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications

An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition to silicided poly for local interconnection, this technology offers four layers of metallization with chemical vapor deposition (CVD) tungsten-filled contacts and vias. Interconnection delays are 1 ps/mil. ABiC technology is most attractive for high-performance 50K to 100K gate ECL logic arrays, 100K to 200K gate CMOS/BiCMOS logic arrays, and high-density ASIC products requiring embedded memories

A 0.8 mu m advanced single poly BiCMOS technology for high density and high performance applications

A single poly, 0.8 mu m BiCMOS technology having both high-performance CMOS and 14 GHz ASPECT III n-p-n transistors is described. The advanced features of this BiCMOS technology include a low encroachment, defect-free recessed oxide isolation process, self-aligned integrated well taps for MOS devices, double diffused bipolar process, silicided local interconnect, and four levels of metallization with tungsten plugs. Ring oscillator gate delays of <150 ps BiCMOS, <90 ps CMOS, and<50 ps ECL are obtained with this process. This technology is most applicable to high-performance/high-density standard cell ECL gate array circuits requiring embedded memory.<<ETX>>

A 2.5 ns ECL 16*16 multiplier

A 16*16 b integer multiplier is described that has achieved a measured delay of less than 2.5 ns, register to register, for a full 16*16 multiply. It was fabricated using ASPECT 3, a 0.8 mu m bipolar process with silicided polysilicon and four-level metallization. A standard cell methodology using an automated sizing and scaling approach was used. In register-to-register mode the worst case clock period is 2.495 ns, with a measured pin-to-pin flow thru mode latency time of 3.37 ns. The I/O delay plus register setup is 875 ps.<<ETX>>

Submicron BiCMOS technologies for supercomputer and high speed system implementation

Submicron process technologies that allow a full implementation of CPU, first-level cache, second-level cache, and the main memory in the BiCMOS approach are described. CPU standard cells up to 100 K ECL gate density with embedded CMOS and BiCMOS SRAM, X9 cache memories, and 1-Meg ECL I/O SRAMs with less than 7-ns access time have been achieved.<<ETX>>

A 30000 gate ECL gate array using advanced single poly technology and four level metal interconnect

The architecture and fabrication of a 30000 emitter coupled logic (ECL) gate array featuring a 90-ps unloaded gate delay are described. Current mode logic (CML) and ECL macros can be combined on custom-defined chips to minimize power without compromising the performance. The product has a channelless ocean-of-cells architecture permitting 100% cell utilization with ECL 100 K and 10 K I/O interface. The gate array is fabricated using ASPECT-II (advanced single poly emitter coupled technology) with silicided polysilicon local interconnect and four-level metallization.<<ETX>>

Application of lightly doped buried-layer for the reduction of the interconnection and junction capacitances

Interconnection delay plays a dominant role in determining the speed performance of todays integrated circuits. It is shown that the formation of a lightly doped buried layer (LDBL) reduces the capacitance of wiring leads and bonding pads with respect to the substrate. LDBL also improves the collector-to-substrate capacitance of npn transistors as well as the tub-to-substrate capacitance of MOS transistors. As a result the speed performance of the products employing this technique is significantly improved. Because of the relative simplicity of the process, the ratio of percent delay reduction to percent cost increase is expected to be smaller than for any alternative approach.<<ETX>>