Ricky Shi Wei Lee

3D LED and IC wafer level packaging

Purpose – The purpose of this paper is to propose new 3D light emitting diodes (LED) and integrated circuits (IC) integration packages.Design/methodology/approach – These packages consist of the multi‐LEDs and active IC chip such as the application specific IC, LED driver, processor, memory, radio frequency, sensor, or power controller in a 3D manner. The assembly processes of these packages are also presented and discussed.Findings – The advantages of these 3D integration packages are found to be: better performance, lower cost, less footprint, lighter package, and smaller form factor.Originality/value – A thermal management system for 3D IC and LEDs integration packages is proposed.

Wafer level LED packaging with integrated DRIE trenches for encapsulation

A novel encapsulation process for wafer level LED arrays is presented. In this process, 4 inch P-type single crystal silicon wafers served as the substrates for flip-chip mountable LED chips. The wafer substrates were fabricated by wafer level lithography and plating process. An UV curable epoxy was applied as the encapsulant. The encapsulation process takes advantage of square trenches fabricated by deep reaction ion etching (DRIE) process as barriers to limit the spread of the epoxy encapsulant, and can adjust the geometry of the encapsulation via controlling the volume of the epoxy and the dimension of the trenches. The packaging and encapsulation process of LED arrays were completed on wafer level. LED packages can be directly obtained after wafer dicing.

Integration of phosphor printing and encapsulant dispensing processes for wafer level LED array packaging

Phosphor converted LEDs (pc-LEDs), which employ blue LEDs with yellow phosphor deposition to generate white light illumination is a widely used solid-state lighting source. This paper presents the integration of two major processes, namely, phosphor screen printing and moldless encapsulant dispensing, for wafer level pc-LED packaging. In the present study, the processing procedures and parameters of phosphor screen printing were developed and investigated in detail. The attributes of the phosphor layer by screen printing such as packing density, thickness, uniformity and adhesive strength, which control the performance of final white light illumination, were characterized. Subsequently a moldless encapsulant dispensing process was applied at the wafer level. Optical performance of the packaged LEDs was evaluated. The prototype of 5×5 white light LED arrays demonstrated that a wafer level LED packaging can be achieved with the integration of the two novel processes.

Reliability study and failure analysis of fine pitch solder-bumped flip chip on low-cost flexible substrate without using stiffener

In flip chip on flex (FCOF) technology, the flexible substrate and the assembly process are essential for the reliability of solder joints. In this research, fine-pitch solder-bumped chips with various chip sizes were assembled on flexible substrates using FCOF technology. The five types of layout design were evaluated for their effects on the assembly process and reliability of FCOF technology. It was found that appropriate substrate layout designs provided more accurate control of the wetting area because they minimized the misalignment between the copper pad and the solder mask opening. The concept of wetting area error ratio is introduced to evaluate the variation of the wetting area on the various layout designs. The shapes of solder joints formed are also related to the flex designs. Die shear test was performed for the samples of FCOF without underfill materials to study the adhesion strength of the copper pad, the solder mask and the base layer. The failed samples after thermal cycling and HAST were analyzed using SAM, an X-ray imaging system, cross-sectioning, and scanning electron microscopy (SEM).

Moldless encapsulation for LED wafer level packaging using integrated DRIE trenches

Abstract This paper demonstrates a LED wafer level packaging process which employs the glob-top dispensing technique for encapsulation. The process utilizes the constraint effect introduced by the trenches to limit the spreading of encapsulant. This enables the geometry control of encapsulation. Several design and process parameters have been investigated. The study has considered the effect of the trench patterns. A 4-in. silicon wafer is fabricated with a pattern etched by the DRIE process. It serves as a substrate for an LED array employed in the present study. Using the wafer substrate and the glop-top dispensing technique, wafer level LED packaging incorporated with a moldless encapsulation process is realized.

LED packaging using silicon substrate with cavities for phosphor printing and copper-filled TSVs for 3D interconnection

A novel wafer level packaging process for phosphor converted LED is presented in this paper. The core of this process is the fabrication of a silicon substrate with cavities for phosphor printing and through-silicon copper pillars for 3D interconnection. A double-side polished 4-inch wafer is used as the substrate. In the present process, DRIE is applied to the back side of the silicon wafer firstly for forming blind vias. The next step is to perform DRIE from the front side to create cavities for LED chip mounting and phosphor printing. Copper is then electroplated to fill the blind vias to form copper pillars. After the copper plating, KOH etching is applied to the front side to further etch the cavities in order to expose the embedded copper pillars. Afterwards, solder is plated on the exposed tips of copper pillars at the bottom of the cavities. Finally, the copper overburden on the back side of the wafer is patterned as the redistribution layer for the next level of interconnection. Subsequent to the fabrication of silicon substrate, blue LEDs are flip-chip mounted on the pre-plated solder bumps in the cavities. Reflow soldering is then conducted to fix the LED chips. Following an epoxy dispensing process, yellow phosphor powder is printed into the cavity for color tuning. The pre-dispensed epoxy is then UV-cured to serve as the phosphor powder binder and the LED chip encapsulant. The present configuration offers a structure with low profile and compact footprint for LED wafer level packaging. The fabrication process is described in detail in this paper.

Characterization of intermetallic compound formation and copper diffusion of copper wire bonding

The trend to replace Au and Al wires with Cu in wire bonding has become an emerging trend for IC packaging nowadays. Although some research works have been carried out for the applications of Cu wire bonding, they are mainly focused on the processing and material issues of Cu wire bonds. However, the Cu in the wire bonds may diffuse into the Si chip and impose reliability threats to the silicon devices. There is no study yet on the Cu-to-Si diffusion in Cu wire bonding. In the present study, the intermetallic compound (IMC) growth in the wire bond and the Cu-to-Si diffusion behavior are investigated. The correlation between IMC growth and Cu diffusion is established. From the experimental characterization, it is found that the IMC growth of Cu-Al is less severe than that of Au-Al. On the other hand, it is also found that the depth of Cu-to-Si diffusion is much larger than that of Au-to-Si. Furthermore, the barrier layer appears to be effective for reducing the Cu and Au diffusion depth in silicon. Nevertheless, it seems that the barrier layer also promotes the growth of IMC in the wire bond. Detailed comparison and discussion of results will be given

Study on copper plating solutions for fast filling of through silicon via (TSV) in 3D electronic packaging

Copper electrodeposition in acidic cupric methanesulfonate electrolyte with organic additives was discussed in this study. The influence of the additives in acidic cupric methanesulfonate bath was studied by means of electrochemical measurement using a rotary electrode and actual TSV copper depositions. The electrochemical parameters including exchange current density and cathodic transfer coefficient of base cupric methanesulfonate electrolyte were successfully determined. Chronoamperometry (CA) was conducted to verify the diffusion time of additives to the surface of electrodes and the corresponding diffusion constants were characterized.

Detailed investigation on the creep damage accumulation of lead-free solder joints under accelerated temperature cycling

Though being accepted and widely employed for decades, there remains no consensus in the industry on the selection of an optimum temperature profile for the accelerated temperature cycling (ATC) test for the evaluation of board level solder joint reliability. It is generally agreed that broader temperature range and higher mean temperature should result in shorter thermal fatigue life. Yet, people have different opinions on the selection of the ramp rate and the dwell time. It was believed that the ramp rate has little influence on the solder joint thermal fatigue life. Emphasis has been put on the design of a suitable dwell time. Therefore, the JEDEC and the IPC standards did not impose strict requirements on the selection of the ramp rate. On the other hand, a certain range of dwell times were recommended. Nevertheless, there were publications showing that the ramp rate may be important and, in some situations, may even overrule the dwell time. This study attempts to investigate in detail the creep damage accumulation inside the solder joint during the ramp time and the dwell time for all practical loading conditions. Based on numerous computational simulation results, the present study reveals that there actually exist two types of creep damage accumulation. One of them corresponds to a “mild” loading condition where the creep damage is mostly accumulated during the dwell time. Another one corresponds to a “severe” loading condition in which the ramp time contributes most of the creep damage accumulation.

Stress Analysis of Hygrothermal Delamination of Quad Flat No-lead (QFN) Packages

Interfacial delamination is the major reliability issue of Quad Flat No-lead (QFN) packages under the JEDEC-MSL preconditioning and reflow process. Failures will occur when the hygrothermal stress exceeds the interfacial strength. Simulation based on finite element model is a popular method for studying the failure mechanism. However, the non-accurate material properties and lack of experiment validations always constrain the Finite Element Analysis (FEA) at the artificial parametric study stage. To further investigate the interfacial delamination, a complex system both including simulation and experiment validation is established in this study. A dummy QFN is fabricated first as the test vehicle for subsequent study. Then the related finite element model is also built up to reveal the interfacial stress distribution when the packages are subjected to the pure thermal loading and hygrothermal loading. Once the interfacial stress is derived, the strength approach is applied here to indicate the high risk area where delamination will occur. Finally, the analyses from simulation are verified by Moisture Sensitivity Level (MSL) tests using dummy samples. In this paper, a superposition method is used to integrate the thermo-mechanical and hygro-mechanical stress together, considering the non-uniform moisture distribution during reflow. The shear stress is found to be dominated along all the interfaces. From the comparison between simulation and experiments, the strength approach is applied to evaluate the package reliability successfully. Both simulation and experiment results show that the molding compound/leadframe interface around the junction of die attach fillet would be the initiation of delamination.